• Journal of KIISE:Computer Systems and Theory
• /
• v.28 no.11
• /
• pp.592-600
• /
• 2001

To improve the performance of wide-issue Superscalar microprocessors, it is essential to increase the width of instruction fetch and issue rate. Data dependences are major hurdle to exploit ILP(Instruction-Level Parallelism) efficiently, so several related works have suggested that the limits imposed by data dependences can be overcome to some extent with the use of the data value prediction. But the suggested mechanisms may access the same value prediction table entry again before they have been updated with a real data value. They will cause incorrect value prediction by using stable data and incur misprediction penalty and lowering performance. In this paper, we propose a new hybrid value predictor which achieve high performance by reducing stale data. Because the proposed hybrid value predictor can update the prediction table speculatively, it efficiently reduces the number of mispredicted instruction due to stable due to stale data. For SPECint95 benchmark programs on the 16-issue superscalar processors, simulation results show that the average prediction accuracy increase from 59% for non-speculative update to 72% for speculative update.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.5
• /
• pp.889-896
• /
• 2007

Advances in wireless networking, micro-fabrication and integration, and embedded microprocessors have enabled a new generation of massive-scale sensor networks. Because each sensor node is limited in size and capacity, it is very important to design a new simple and energy efficient protocol. Among conventional sensor networks' routing protocols, the directed diffusion scheme is widely blown because of its simplicity. This scheme, however, has a defect in that sending interest and exploratory data messages while setting connection paths consumes much energy because of its flooding scheme. Therefore, this paper proposes a new sensor network routing protocol, called sequenced directed diffusion with a threshold control, which compromises the conventional directed diffusion scheme's defect and offers an energy efficient routing idea. With a computer simulation, its performance is evaluated and compared to the conventional directed diffusion scheme. Numerical results show that the proposed scheme offers energy efficiency while routing packets, and resolves ill-balanced energy consumption among sensor nodes.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.18 no.3
• /
• pp.9-21
• /
• 2008

In this paper, we revisit a generally accepted opinion: implementing Elliptic Curve Cryptosystem (ECC) over GF$(2^m)$ on sensor motes using small word size is not appropriate because partial XOR multiplication over GF$(2^m)$ is not efficiently supported by current low-powered microprocessors. Although there are some implementations over GF$(2^m)$ on sensor motes, their performances are not satisfactory enough due to the redundant memory accesses that result in inefficient field multiplication and reduction. Therefore, we propose some techniques for reducing unnecessary memory access instructions. With the proposed strategies, the running time of field multiplication and reduction over GF$(2^{163})$ can be decreased by 21.1% and 24.7%, respectively. These savings noticeably decrease execution times spent in Elliptic Curve Digital Signature Algorithm (ECDSA) operations (Signing and verification) by around $15{\sim}19%$.

• Journal of the Society of Disaster Information
• /
• v.18 no.4
• /
• pp.699-705
• /
• 2022

Purpose: Sequence control is widely used by being applied to manufacturing, distribution, construction, and automation in the medical industry. With the development of the fourth industry, artificial intelligence convergence technology in the control field is becoming an important factor in the industry. In particular, it is required to evaluate the safety and innovation of facilities where microprocessors and artificial intelligence are fused to existing systems and develop reliable equipment, so it is intended to develop equipment for educational purposes and drive the development of the field. Method: The self-developed all-in-one artificial intelligence controller module is a device that combines artificial intelligence capabilities with existing sequence and PLC control circuits. As the performance evaluation items of this equipment, the recognition ability of motion, voice, text, color, etc. and the stability and reliability of the circuit were evaluated. Conclusion: After designing the sequence and PLC circuit, the performance evaluation items of the integrated integrated artificial intelligence controller module were all satisfied, and there was no problem in the safety and reliability of the circuit.

• Journal of the Korea Society of Computer and Information
• /
• v.14 no.1
• /
• pp.145-151
• /
• 2009

There are excessively hot units of a microprocessor in today's nano-scale process technology, which are called hotspots. Hotspots' heat dissipation is not perfectly conquered by mechanical cooling techniques such as heatsink, heat spreader, and fans; Hence, an architecture-level temperature simulation of microprocessors is evident experiment so that designers can make reliable chips in high temperature environments. However, conventional thermal simulators cannot be used in temperature evaluation of real machine, since they are too slow, or too coarse-grained to estimate overall system models. This paper proposes methodology of monitoring accurate runtime temperature with Hotspot[4], and introduces its implementation. With this tool, it is available to track runtime thermal behavior of a microprocessor at architecture-level. Therefore, Dynamic Thermal Management such as Dynamic Voltage and Frequency Scaling technique can be verified in the real system.

• Journal of IKEEE
• /
• v.28 no.3
• /
• pp.337-341
• /
• 2024

As the production process for silicon-based integrated circuits approaches physical limits, a lot of attention is focused on the new semiconductor materials to overcome these problems. Carbon NanoTubes(CNTs) are attracting a lot of interest as one of the most competitive materials with excellent electrical transport and scaling properties, and CNTFETs using CNTs are gaining popularity as next-generation semiconductor devices. However, since the technology to place CNTs in a certain direction and interval on the wafer is not yet mature enough, it is difficult to construct all necessary circuits with CNTFET only. So, there is increasing interest in a hybrid configuration using MOSFET and CNTFET together. Because SRAM plays a role as a cache in microprocessors and is a critical circuit block influencing microprocessor performance, research to implement existing SRAM in a hybrid form is steadily progressing. Therefore, in this paper, we will explain the design method of hybrid 8T SRAM based on the existing hybrid 6T SRAM and discuss the performance difference between the two circuits.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.7
• /
• pp.454-461
• /
• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.48 no.3
• /
• pp.82-90
• /
• 2011

Multi-core system is becoming more general with development of microprocessors. Due to this change in performance improvement paradigm, switching conventional single thread applications with multi thread applications. Performance monitoring tools are used to optimize application performance because of complexity in development of multi thread applications. Conventional performance monitoring tools are focused on performance itself rather than user friendliness or real-time support. Real-time performance monitor identify the problem while multi-threaded applications should be performed as well as check real-time operating status of the application. So it can be used as an effective tool compared to non-real-time performance monitor that only with simple performance indicators to find the cause of the problem. In this paper, we propose RMPM(Real-time Multi-core Performance Monitor) which is real-time performance monitoring tool for multi-core system. Observation period is optimized by comparing relation between overhead due to performance evaluation period and accuracy. Our performance monitor shows not only amount of CPU usage of whole system, memory usage, network usage but also aspect of overhead distribution per thread of an application.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.3
• /
• pp.249-255
• /
• 2017

The finger vein recognition technology is a method to acquire a finger vein image by illuminating infrared light to the finger and to authenticate a person through processes such as feature extraction and matching. In order to recognize a finger vein, a 2D mask-based two-dimensional convolution method can be used to detect a finger edge but it takes too much computation time when it is applied to a low cost micro-processor or micro-controller. To solve this problem and improve the recognition rate, this study proposed an extraction method for the region of interest based on virtual core points and moving average filtering based on the threshold and absolute value of difference between pixels without using 2D convolution and 2D masks. To evaluate the performance of the proposed method, 600 finger vein images were used to compare the edge extraction speed and accuracy of ROI extraction between the proposed method and existing methods. The comparison result showed that a processing speed of the proposed method was at least twice faster than those of the existing methods and the accuracy of ROI extraction was 6% higher than those of the existing methods. From the results, the proposed method is expected to have high processing speed and high recognition rate when it is applied to inexpensive microprocessors.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1332-1339
• /
• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.