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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Study on the Design Methodology for Hybrid 8T SRAM

Hybrid 8T SRAM 설계 방법에 관한 연구

  • Geunho Cho (Department of Electronic Engineering, Seokyeong University)
  • 조근호
  • Received : 2024.08.09
  • Accepted : 2024.09.19
  • Published : 2024.09.30
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Abstract

As the production process for silicon-based integrated circuits approaches physical limits, a lot of attention is focused on the new semiconductor materials to overcome these problems. Carbon NanoTubes(CNTs) are attracting a lot of interest as one of the most competitive materials with excellent electrical transport and scaling properties, and CNTFETs using CNTs are gaining popularity as next-generation semiconductor devices. However, since the technology to place CNTs in a certain direction and interval on the wafer is not yet mature enough, it is difficult to construct all necessary circuits with CNTFET only. So, there is increasing interest in a hybrid configuration using MOSFET and CNTFET together. Because SRAM plays a role as a cache in microprocessors and is a critical circuit block influencing microprocessor performance, research to implement existing SRAM in a hybrid form is steadily progressing. Therefore, in this paper, we will explain the design method of hybrid 8T SRAM based on the existing hybrid 6T SRAM and discuss the performance difference between the two circuits.

실리콘 기반 집적회로의 제조 공정이 물리적 한계에 가까워짐에 따라 이를 극복하기 위한 반도체 물질에 많은 관심이 집중되고 있다. 탄소나노튜브(CNT)는 우수한 전기 수송 및 스케일링 특성을 가진 가장 경쟁력 있는 소재 중 하나로 많은 관심을 받고 있으며, 이러한 CNT를 활용한 CNTFET은 차세대 반도체 소자로 많은 인기를 얻고 있다. 하지만, CNT를 웨이퍼 위에 일정한 방향과 간격으로 배치시키는 기술이 아직 충분히 성숙하지 않아 CNTFET만으로 필요한 모든 회로를 구성하기에는 어려움이 있다. 따라서, MOSFET과 CNTFET을 함께 사용하는 hybrid 구성에 관심이 커지고 있다. SRAM은 마이크로프로세서에서 캐시 역할을 하며 마이크로프로세서 성능에 중요한 영향을 미치는 회로블록이기 때문에 기존 SRAM을 hybrid 형태로 구현하고자 하는 연구가 꾸준히 진행되고 있다. 따라서, 본 논문에서는 기존의 hybrid 6T SRAM을 기반으로 hybrid 8T SRAM 디자인 방법에 대해 설명하고 두 회로 사이의 성능차에 대해 논의하고자 한다.

Keywords

Acknowledgement

This Research was supported by Seokyeong University in 2024. The EDA tool was supported by the IC Design Education Center(IDEC), Korea

References

  1. F. Zahoor et al., "Carbon nanotube field effect transistors: an overview of device structure, modeling, fabrication and applications," Physica Scripta, vol.98, 2023. DOI: 10.1088/1402-4896/ace855 
  2. G. Fan et al., "Physics-integrated machine learning for efficient design and optimization of a nanoscale carbon nanotube field-effect transistor," ECS Journal of Solid State Science and Technology, vol.12, 2023. DOI: 10.1149/2162-8777/acfb38 
  3. Y. Kim et al., "A novel CNFET SRAM-based compute-in-memory for BNN considering chirality and nanotubes," Electronics, vol.13, 2024. DOI: 10.3390/electronics13112192 
  4. J. Cui et al., "Carbon nanotube integrated circuit technology: purification, assembly and integration," International Journal of Extreme Manufacturing, vol.6, 2024. DOI: 10.1088/2631-7990/ad2e12 
  5. S. Jayanthi et al., "Single-ended 12T CNTFET SRAM cell with high stability for low power smart device applications," e-Prime - Advances in Electrical Engineering, Electronics and Energy, vol.7, 2024. DOI: 10.1016/j.prime.2024.100479 
  6. M. Elangovan et al., "Effect of CNTFET parameters on novel high stable and low power: 8T CNTFET SRAM cell," Transactions on Electrical and Electronic Materials, vol.23, 2022. DOI: 10.1007/s42341-021-00346-9 
  7. M. U. Mohammed et al., "A disturb free read port 8T SRAM bitcell circuit design with virtual ground scheme," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, 2018. DOI: 10.1109/MWSCAS.2018.8624107 
  8. A. Teman et al., "A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM)," IEEE Journal of Solid-State Circuits, vol.46, 2011. DOI: 10.1109/JSSC.2011.2164009 
  9. N. Verma et al., "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy," IEEE Journal of Solid-State Circuits, vol.43, 2008. DOI: 10.1109/JSSC.2007.908005 
  10. L. Chang et al., "Stable SRAM cell design for the 32 nm node and beyond," Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. DOI: 10.1109/.2005.1469239 
  11. Y. Li et al., "Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning," Nature Communications, 2023. DOI: 10.1038/s41467-023-42981-1 
  12. G. Cho, "A Study on the Design Method of Hybrid MOSFET-CNTFET based SRAM," Journal of IKEEE, vol.27, 2023. DOI: /10.7471/ikeee.2023.27.1.65 
  13. Y. Cao et al., "Predictive technology model for nano-CMOS design exploration," 2006 1st International Conference on Nano-Networks and Workshops, 2006. DOI: 10.1109/NANONET.2006.346227 
  14. CNFET Models. https://nano.stanford.edu/downloads/stanford-cnfet-model/stanford-cnfet-model-hspice 
  15. G. Hills et al., "Modern microprocessor built from complementary carbon nanotube transistors," Nature, 2019. DOI: 10.1038/s41586-019-1493-8 
  16. Anantha Chandrakasan et al., "Design of High-Performance Microprocessor Circuits," Wiley-IEEE Press, 2000.