• Title/Summary/Keyword: Carbon Nabotube

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A Study on the Design Method of Hybrid MOSFET-CNTFET based SRAM (하이브리드 MOSFET-CNTFET 기반 SRAM 디자인 방법에 관한 연구)

  • Geunho Cho
    • Journal of IKEEE
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    • v.27 no.1
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    • pp.65-70
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    • 2023
  • More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and various CNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductor chip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discusses a methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAM or CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM and compare its performance with the conventional MOSFET SRAM and CNTFET SRAM.

A Study on the Effect of Process Variation on the Performance of Hybrid MOSFET-CNTFET based SRAM (공정 편차가 하이브리드 MOSFET-CNTFET 기반 SRAM의 성능에 미치는 영향에 대한 연구)

  • Geunho Cho
    • Journal of IKEEE
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    • v.27 no.3
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    • pp.327-332
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    • 2023
  • CNTFET, which is receiving high attention as a next-generation semiconductor candidate due to its higher performance and various utilization than traditional silicon-based semiconductor devices, is having difficulty in commercialization because its unique process deviation such as CNT placement has not yet matured. To overcome this difficulty, numerous studies have been continuously conducted to take advantages of CNTFET and compensate its weakness by implementing circuits, which are less affected by process deviation due to repetitive circuit placement, into MOSFET-CNTFET based hybrid circuits. This paper compares how much the performance of the hybrid SRAM can be changed by semiconductor process variation existing in the traditional MOSFET SRAM or CNTFET SRAM. Simulation results show that, if the CNT density can be maintained between 7 and 9 per 32nm, hybrid SRAM is about 2.6 times and about 1.1 times more robust to process deviation than conventional MOSFET SRAM in read and write operations, respectively.