• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• Proceedings of the Korean Nuclear Society Conference
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• 1995.05a
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• pp.602-607
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• 1995

This article presents safety review experience of microprocessor-based Interposing Logic System(ILS) of Engineering Safety Feature Actuation System(ESFAS). The ILS is the first application of computerized logic design to safety system in Korean nuclear power plants without verification of the system reliability by proven technology concept. As a result of evaluation for the ILS, Korea Institute of Nuclear Safety(KINS) concluded that the microprocessor-based ILS is not acceptable in some features detailed enough to defend against software common mode failures(CMF). Therefore, we required licensee to install hardwired interlock signal configuration and a Hardwired Backup Panel to control safety-related equipment. We believe that the microprocessor-based ILS with the hardwired backup panel and inter-connection of interlock signal by hardwired configuration will improve the plant safety.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.423-428
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• 2010

In the initial design phase of superscalar microprocessors, a performance model is necessary. A theoretic performance model is very useful since performance for various architecture parameters can be obtained by simply computing equations, without repeating simulations, Previous studies established theoretic performance models using the relation between the instruction window size and the issue width, with the penalties due to branch mispredictions and cache misses. However, the study was intended for unlimited number of functional units, which is insufficient for the real case application. This paper proposes a superscalar microprocessor theoretical performance model which also works for the limited functional units. To enhance the accuracy of our limited functional unit model, instruction dependency rates are employed. By using trace-driven data of SPEC 2000 integer programs as input, this paper shows that the theoretically computed performance of superscalar microprocessor with limited number of functional units is quite similar to the measured performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.04a
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• pp.893-895
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• 2016

세계적으로 헬스케어 산업의 발전 가능성은 눈에 띄게 증가하고 있다. 그 중에서도 환자 혹은 각종 디바이스 사용자의 생체신호를 다루는 기술은 다양한 중요정보를 얻을 수 있다. 본 논문에서는 심전도의 미세한 생체 전위를 측정하기 위해 각종 필터와 증폭기를 이용하여 회로를 설계하고 이를 Cortex-M3 Microprocessor와 MATLAB 프로그램을 이용하여 필터링과 데이터통신을 통해 최종적으로 실시간으로 모니터링 하였다. 일반적으로 임상이나 진단에 이용되는 ECG 신호는 각종 심장질환의 지표로 사용되지만 전문적인 지식을 갖추지 않은 일반 사용자가 사용하기에는 어려운 점이 없지 않아 있다. 따라서 이 연구는 아날로그 신호를 디지털 신호로 변환하여 생체신호를 다루는 다양한 분야에서 용이할 수 있다.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.303-305
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• 1993

Walsh function and transform are important analytical tools for control theory and signal processing and have wide applications in those fields, especially in the field of digital communications. Therefore there is a need for a Walsh function generator in order to realize certain applications. And a number of different desists are known. But desist and implementation of such a generator through hardware logic nay give rise to orthogonality error. To develop Walsh function generator which gets rid of orthogonality error, this paper presents a microprocessor based design and implementation method.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.4 no.2
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• pp.29-33
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• 1986

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.82-86
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• 1989

In this paper, digital autopilot design methods are investigated and a new method is suggested in order to improve existing problems. The method is based on .delta. transform (1) and overcome numerical problems occurring in the process of discretization. We illustrate design procedures using .delta. transform and suggest a hardware and software structure for digital autopilot implemented by microprocessor.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.31-39
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• 2004

The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.35-40
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• 2023

In this paper, a serial wireless LAN virtual communication module that allows microprocessors to communicate wirelessly with other peripheral devices is developed as part of a study to build an online virtual experiment system that allows them to practice virtually anytime, anywhere in microprocessor application education in electrical and electronic control engineering. The developed module is connected to the microprocessor in the virtual experiment system through serial interface. The serial data is sent to and received from peripheral devices through the wireless LAN interface of the host computer where the virtual experiment software is being performed. In order to verify the function of the developed serial wireless LAN virtual communication module, experiments were conducted in which a microprocessor in the virtual experiment system exchanged data with an Android smartphone through a wireless LAN interface of a host computer. The developed serial wireless LAN communication module is expected to enable virtual microprocessors to communicate with surrounding real devices through wireless LAN, which can be efficiently used in microprocessor application education.