• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.68-76
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• 2010

Touch-enabled technology is increasingly being accepted as a main communication interface between human and computers. However, conventional touchscreen technologies, such as resistive overlay, capacitive overlay, and SAW(Surface Acoustic Wave), are not cost-effective for large screens. As an alternative to the conventional methods, we introduce a newly emerging method, an optical imaging touchscreen which is much simpler and more cost-effective. Despite its attractive benefits, optical imaging touchscreen has to overcome some problems, such as heavy computational complexity, intermittent ghost points, and over-sensitivity, to be commercially used. Therefore, we designed a hardware controller for signal processing and multi-coordinate computation, and proposed Infrared-blocked DA(Dark Area) manipulation as a solution. While the entire optical touch control took 34ms with a 32-bit microprocessor, the designed hardware controller can manage 2 valid coordinates at 200fps and also reduce energy consumption of infrared diodes from 1.8Wh to 0.0072Wh.

• Korean Journal of Agricultural Science
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• v.22 no.1
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• pp.24-41
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• 1995

The objective of this study were to review and analyze the application technologies of electronics and microprocessor for environment control and automated management systems of livestock production of the advanced countries, and to select the appropriate and applicable technologies for our systems among the analyzed. In this study, the environment control systems were analyzed mainly on the poultry production systems; and the automated management systems on swine and dairy production systems. According to the results, the advanced technologies reviewed and analyzed could be applicable for designing our animal production systems, if those were modified and remodeled for our situation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.6
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• pp.1381-1387
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• 2007

Up to now, various continuous-processing systems are used in many industrial applications such as textile machines, paper-making machines, printing machines, and so on. In these applications, the tension forced on the products in the control volume can be changed according to the velocity difference between the feeding roll and the delivery roll. Specially, the tension variation generated by the velocity difference, or the inertial effect can decreases the quality of the products in the textile process. In this paper, the tension control problem in a circular knitting machine system is treated to cope with these problems. Firstly, the tension relationship in the winding mechanism of general continuous-processing systems is modeled. Next, to effectively drive the feeding and delivery rolls in the circular knitting machine system, a new tension control method is presented by considering the inertia compensation and the velocity difference between the feeding roll and the delivery roll. Through the experimental works, it is shown that the proposed tension control method can be used to improve the performance of tension control in the control volume of the given circular knitting machine system.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.347-356
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• 2009

Precise branch prediction is a critical factor in the IPC Improvement of modern microprocessor architectures. In addition to the branch prediction accuracy, branch prediction delay have a profound impact on overall system performance as well. However, it tends to be overlooked when the architects design the branch predictor. To tolerate branch prediction delay, this paper proposes Early Start Prediction (ESP) technique. The proposed solution dynamically identifies the start instruction of basic block, called as Basic Block Start Address (BB_SA), and the solution uses BB_SA when predicting the branch direction, instead of branch instruction address itself. The performance of the proposed scheme can be further improved by combining short interval hiding technique between BB_SA and branch instruction. The simulation result shows that the proposed solution hides prediction latency, with providing same level of prediction accuracy compared to the conventional predictors. Furthermore, the combination with short interval hiding technique provides a substantial IPC improvement of up to 10.1%, and the IPC is actually same with ideal branch predictor, regardless of branch predictor configurations, such as clock frequency, delay model, and PHT size.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.53-60
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• 2002

This paper describes a Gray Mode Graphic STN LCD drive circuit using USB interface. The drive circuit using USB interface can highly transfer image data created under PC t LCD. Hence, the LCD drive circuit doesn't use microprocessor for the convenience of users. The proposed LCD drive circuit part have been verified by simulation and by ALTERA EPF10K10TC144-3 FPGA implementation in VHDL. The USB interface part have been programmed in MS-Visual C++ 6.0. The validity and efficiency of the proposed LCD drive circuit have been verified by test board. After comparing this LCD drive circuit to specify it was verified that the developed LCD drive circuit showed good performances, such as convenience of users, low cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.1976-1979
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Smart Structures and Systems
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• v.2 no.2
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• pp.115-126
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• 2006

The Terra-Scope system is an affordable 4-D down-hole seismic monitoring system based on independent, microprocessor-controlled sensor Pods. The Pods are nominally 50 mm in diameter, and about 120 mm long. They are expected to cost approximately $6000 each. An internal 16-bit, extremely low power MCU controls all aspects of instrumentation, eight programmable gain amplifiers, and local signal storage. Each Pod measures 3-D acceleration, tilt, azimuth, temperature, and other parametric variables such as pore water pressure and pH. Each Pod communicates over a standard digital bus (RS-485) through a completely web-based GUI interface, and has a power consumption of less than 400 mW. Three-dimensional acceleration is measured by pure digital force-balance MEMS-based accelerometers. These accelerometers have a dynamic range of more than 115 dB and a frequency response from DC to 1000 Hz with a noise floor of less than $30ng_{rms}/{\surd}Hz$. Accelerations above 0.2 g are measured by a second set of MEMS-based accelerometers, giving a full 160 dB dynamic range. This paper describes the system design and the cooperative shared-time scheduler implemented for this project. Restraints accounted for include multiple data streams, integration of multiple free agents, interaction with the asynchronous world, and hardened time stamping of accelerometer data. The prototype of the device is currently undergoing evaluation. The first array will be installed in the spring of 2006.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.3
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• pp.27-35
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• 2011

Design of Sensor nodes in Wireless Sensor Network(WSN) should be considered some properties as electricity consumption, transmission speed, range, etc., and also be needed the protection against various attacks (e.g., eavesdropping, hacking, leakage of customer's secret data, and denial of services). The stream cipher Rabbit, selected for the final eSTREAM portfolio organized by EU ECRYPT and selected as algorithm in part of ISO/IEC 18033-4 Stream Ciphers on ISO Security Standardization recently, is a high speed stream cipher suitable for WSN. Since the stream cipher Rabbit was evaluated the complexity of side-channel analysis attack as 'Medium' in a theoretical approach, thus the method of power analysis attack to the stream cipher Rabbit and the verification of our method by practical experiments were described in this paper. We implemented the stream cipher Rabbit without countermeasures of power analysis attack on IEEE 802.15.4/ZigBee board with 8-bit RISC AVR microprocessor ATmega128L chip, and performed the experiments of power analysis based on difference of means and template using a Hamming weight model.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.