• Title/Summary/Keyword: Microprocessor design

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A Study on the Design of Water Pollution Alarm System using Solar Cell (솔라셀을 적용한 수질오염 경보 시스템의 설계에 관한 연구)

  • Yoon, Seok-Am;Choi, Jang-Gyun;Yoon, Hyung-Sang;Kim, Min;Lee, Gi-Je;Cha, In-Su
    • Proceedings of the KIPE Conference
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    • 1999.07a
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    • pp.569-572
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    • 1999
  • As the industry has been growing rapidly, the problem of environmental pollution has been on the rise seriously. In this paper, we used solar cells at the power supply unit of the equipment, which has been sold at present, for measuring the quality of water in order to complement the problem. Also, to get rid of the inconvenience that the examiners must go to the job site, check and collect the polluted water we set the goal at designing the water pollution alarm system which measures the quality of water automatically using one-chip microprocessor and materializing the program.

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Assistant Professor, Department of Computer Engineering Pukyong Universisty (한국형 방송 프로그램 시스템 디코더 ASSP의 개발)

  • Jo, Gyeong-Yeon
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.5
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    • pp.1229-1239
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    • 1996
  • The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP (Applicatio n Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared raccoon receiver, async scrial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.

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Timing analysis of RSFQ ALU circuit for the development of superconductive microprocessor (초전도 마이크로 프로세서개발을 위한 RSFQ ALU 회로의 타이밍 분석)

  • Kim J. Y;Baek S. H.;Kim S. H.;Kang J. H.
    • Progress in Superconductivity and Cryogenics
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    • v.7 no.1
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    • pp.9-12
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    • 2005
  • We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

Development of automatic die bonder system for semiconductor parts assembly (반도체 소자용 자동 die bonding system의 개발)

  • 변증남;오상록;서일홍;유범재;안태영;김재옥
    • 제어로봇시스템학회:학술대회논문집
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    • 1988.10a
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    • pp.353-359
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    • 1988
  • In this paper, the design and implementation of a multi-processor based die bonder machine for the semiconductor will be described. This is a final research results carried out for two years from June, 1986 to July, 1988. The mechanical system consists of three subsystems such as bonding head module, wafer feeding module, and lead frame feeding module. The overall control system consists of the following three subsystems each of which employs a 16 bit microprocessor MC 68000 : (i) supervisory control system, (ii) visual recognition / inspection system and (iii) the display system. Specifically, the supervisory control system supervises the whole sequence of die bonder machine, performs a self-diagnostics while it controls the bonding head module according to the prespecified bonding cycle. The vision system recognizes the die to inspect the die quality and deviation / orientation of a die with respect to a reference position, while it controls the wafer feeding module. Finally, the display system performs a character display, image display ans various error messages to communicate with operator. Lead frame feeding module is controlled by this subsystem. It is reported that the proposed control system were applied to an engineering sample and tested in real-time, and the results are sucessful as an engineering sample phase.

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Design of Irrigation Pumping System Controller for Operational Instrument of Articulation (관절경 수술을 위한 관주(灌注)시스 (Irrigation Pumping System) 제어기의 개발)

  • 김민수;이순걸
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2003.06a
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    • pp.1294-1297
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    • 2003
  • With the development of medical field, many kinds of operations have been performed on human articulation. Arthroscopic surgery, which has Irrigation Pumping System for security of operator vision and washing spaces of operation, has been used for more merits than others. In this paper, it is presented that the research on a reliable control algorithm of the pumping system instrument for arthroscopic surgery. Before clinical operation, the flexible artificial articulation model is used for realizing the model the most same as human's and the algorithm has been exploited for it. This system is considered of the following; limited sensing point, dynamic effect by compliance, time delay by fluid flow and so on. The system is composed with a pressure controller, a regulator for keeping air pressure, an airtight tank that can have distilled water packs, artificial articulation and a measuring system, and has controlled by the feedback of pressure sensor on the artificial articulation. Also the system has applied to Smith Predictor for time delay and the parameter estimation method for the most suitable system with both the experiment data and modeling. In this paper, the pressure error that is between an air pressure tank and an artificial articulation was measured so that the system could be presumed and then the controller had developed for performing State-Feedback. Finally, the controller with a real microprocessor has realized. The confidence of system can be proved by applying this control algorithm to an artificial articulation experiment material.

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Remote Measurement of the Automobile′s ECU Signals with KWP2000 using Bluetooth Module (Bluetooth 모듈을 이용한 KWP2000 차량 ECU신호의 원격 계측)

  • Choi Kwang-Hun;Kwon Tae-Kyu;Lee Seong-Cheol
    • Journal of the Korean Society for Precision Engineering
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    • v.21 no.10
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    • pp.86-93
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    • 2004
  • This paper presents the remote measurement of the ECU signals adopted with KWP 2000 protocol using the wireless communication technique of bluetooth. The bluetooth technology will be the most promising network paradigm which can open the new area in the information technology. Especially, bluetooth module is able to link all the electrical products and personal computers to cellular phone or PDA. This research has a try to design a wireless measurement model of ECU signal based on the car telemery system using bluetooth device. In order to measure the ECU signals, we designed the interface circuits which is able to communicate between the ECU system and the terminal circuits according to the ISO, SAE regulation of communication protocol standard. A microprocessor S3c341 OX is used for the system control and communication of ECU signals. The embedded system software is programmed to measure the ECU signals using the ARM compiler and ANCI C based on Micro/OS-II kernel to communicate between two bluetooth modules using bluetooth stack. The remote measurement of ECU signals using the bluetooth was designed and implemented to evaluate the performance of wireless network to the transmit measurement data. The possibility for the remote measurement of the self diagnosis signals of ECU adopted with KWP2000 protocol verified through the developed systems and algorithms in embedded system.

VLSI Design of a Bus Interface Controller for 32-bit RISC microprocessor (32비트 RISC 마이크로프로세서를 위한 버스 인터페이스 제어기의 설계)

  • Heo, Sang-Kyong;An, Sang-Jun;Jeong, Wook-Yeong;Kim, Young-Jun;Lee, Yong-Surk
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.341-344
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    • 1999
  • 본 논문에서는 DSP 기능을 내장한 32비트 RISC 마이크로프로세서를 위한 버스 제어기를 설계하였다. 연구의 초점은 버스 타이밍, 주소 멀티플렉싱, 리프레쉬, 버스 중재 등을 제어하는 버스제어기를 온칩화 하여 CPU로 하여금 외부 램과 추가적인 장치없이 직접 연결될 수 있도록 한 것이다. 버스 제어기가 관리하는 메모리의 종류는 SRAM, ROM, DRAM, EDO DRAM이며 고속 모드(Fast page mode, EDO page mode 및 RAS-down mode)기능을 지원하며 다양한 Wait를 넣을 수 있다. 주소 영역은 4가지(EMAO-EMA3)이며 내부적으로 7개 의 레지스터가 있고 이들을 이용하여 서로 연결된 세 개의 상태 머신으로 모든 램과의 타이밍을 제어함으로써 공유블록을 활용할 수 있었다. Verilog HDL의 기술하고 Synopsys로 합성한 후 타이밍 검증을 수행한 결과 최악조건에서 53.1㎒로 동작할 수 있었다. 그 후 0.6㎛ single poly triple metal process 공정으로 레이아웃 되었고 면적은 44㎜ × 1.21㎜ 이다.

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The Architecture Design of 32-bit RISC Microprocessor with DSP Functional Unit (DSP 기능 유닛을 내장한 32비트 RISC 마이크로프로세서의 구조 설계)

  • An, Sang-Jun;Jeong, Wook-Kyeong;Kim, Moon-Gyung;Moon, Sang-Ook;Lee, Yong-Surk
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.345-348
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    • 1999
  • 본 논문에서는 내장형 응용에 적합한 RISC 마이크로프로세서와 DSP 프로세서의 기능을 유기적으로 결합한 구조를 연구하고 이를 설계한다. 프로그램의 크기를 줄이기 위해 RISC 명령어는 16비트 명령어 집합을 설계하고 분기 명령어로 인한 손실을 줄이기 위해 한 개의 지연 슬롯을 갖고 있다. DSP 명령어는 32비트 길이를 갖고 한 명령어로 곱셈, 덧셈(뺄셈), 두 가지 데이터 이동을 할 수 있어서 한 사이클에 최대 네 가지 동작을 할 수 있다 파이프라인 단계는 IF, ID, EX, MA, WB/DSP의 다섯 단계로 구성된다. DSP 기능을 지원하기 위해 내부 루프 버퍼를 갖고 정수 실행부에서는 주소 발생을 위한 전용 하드웨어와 DSP 유닛에서는 곱셈 및 누적 기능을 지원하기 위한 17 × 17 비트 곱셈기가 내장된다. 제안된 구조의 설계는 Verilog-HDL을 이용하여 top-down 설계 방식으로 설계되었고 각 기능 검증을 마친 후 3.3V, 0.6㎛ CMOS triple metal single poly 공정을 이용하여 합성하고 레이아웃 하였다.

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Design and implementation of low-power VLSI system using software control of supply voltages (소프트웨어 전압 제어를 사용한 저전력 VLSI 시스템의 설계 및 구현)

  • Lee, Seong-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.4
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    • pp.72-83
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    • 2002
  • In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

The Design of Code Detector for Sell Call Radio Buoy (Sell Call Radio Buoy용 코드검출기 설계)

  • Cho, Nae-Soo;Kim, Joo-Hwan;Youn, Kyoung-Seop;Kwon, Woo-Hyen
    • Journal of Sensor Science and Technology
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    • v.20 no.3
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    • pp.199-206
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    • 2011
  • Sell call radio buoy is mostly used for searching for the location of fishing nets. Sell call radio buoy for the detection of the code uses the band pass filter(BPF). All BPF is used by imported from Japanese companies. But, Japanese companies stopped selling buoys for searching for the location of fishing nets, and domestic manufacturing companies could not sell buoys any more. Therefore, In this paper, a new method to replace the conventional buoy code detector is proposed. The proposed methods are constructed with an analog filter division composed of BPFs and notch filters as well as a microprocessor with analog digital converters. The advantage of proposed methods is able to combine various codes, can enhance receiver sensitivity. The experimental results confirm the usefulness of the proposed method.