• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.4B no.4
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• pp.201-205
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• 2004

The CCFL dimming control methods are generally used lamp current regulation or average current adjustment method feeding the CCFL inverter. Inverter operation frequency is higher than resonant frequency for safe operation. In this study, we design the half-bridge type series and parallel resonant converter circuit that switches at variable frequency modulation methods to control the output power. This method has advantages such as low EMI and reduced harmonics, and it is convenient for dimming control using a microprocessor. The validity of this study is confirmed from the simulation and experimental results.

• ETRI Journal
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• v.25 no.6
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• pp.510-516
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• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.5
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• pp.354-360
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• 2003

For the convenient use of high performance microprocessor in motor control, peripheral devices are needed for converting its control signals to compatible ones for motor drive. Customized devices are not plentiful far these purposes and their functions do not usually satisfied designers specification. The designers used to implement these functions on FPGA or CPLD using hardware description language. Then, in this case unessential programs are needed for control the peripherals. In this paper, a unified device model that links peripheral devices, including especially the pulse width modulation controller and the quadrature encoder interface device, to an interrupt controller is proposed. Advanced functions of peripherals could be achieved by this model and unessential programs can be simplified. Block diagrams and flowcharts are presented to illustrate the advanced functions. This unified device was designed using VHDL. The simulation results were presented to demonstrate the effectiveness of the proposed scheme.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.6
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• pp.9-16
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• 2007

This paper describes the design and implementation of the fault diagnosis on the Electronic Throttle Control(ETC) System. The proposed fault diagnosis consists of an input signal, actuator and a processor diagnosis. The input signal diagnosis can detect the faults of the ETC system's input signals such as the position sensor fault, source voltage fault, load current fault, and desired position fault. The actuator diagnosis is able to detect the actuator fault due to the actuator aging and an obstacle which interfere in the movement of the actuator. The processor diagnosis detects the fault which prevents the microprocessor from operating the ETC software. In order to protect the breakdown of the ETC system and assure the driving safety, appropriate reactions are also proposed according to the detected faults. The safety and reliability of the ETC system can be improved by the proposed fault diagnosis.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.5
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• pp.44-52
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• 2007

In this study, design and control method using low cost Micro-controller(MCU) for inverter driving circuit in fluorescence lamp is presented. Soft starting technique is adopted to reduce switching loss and moment deterioration which are induced by high speed switching frequency in inverter ballast. Performance of the ballast stabilizer and the lighting characteristic of the fluorescence lamp have been improved by stabilizing switching pulses through the Pulse Width Modulation control.

• Journal of Power Electronics
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• v.9 no.3
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.52-55
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• 1996

In order to establish the robust current controller design technique of series wound motor driver system. This paper proposes a method of compensated Bang-Bang current control using a series wound motor driver system under improperly variable load. To get minimum time torque control. A compensated Bang-Bang current controller structure is simpler than the structure of PID plus Bang-Bang controller. This paper shows that a general 8 bits microprocessor be used efficiently implementing such an algorithm. The calculation time of software is extremely small when compared with conventional PID plus Bang-Bang a controller. Both nonlinear operating characteristics of Digital switching elements and Describing Function methods are used for the analysis and synthesis. Real time implementation of compensated Bang-Bang current is achieved. Concept design strategy of the control and PWM waveform generation algorithms are presented in the paper.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.6
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• pp.209-216
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• 1986

This paper describes the design of multi channel data acquisiton system for industrial process automation. The prototype hardware assembly consists of Z-80A microprocessor, 10-bit A/D converter with 16-channel analog multiplexor and related interface circuitry. The first order lag filter, which can be implemented without any particular computational problem has implemented in software, and the simulation results are shown. The protype system can communicate with a central processor through RS-232C, and can be used either as an intelligent stand-alone controller or as a satellite controller which can be monitored and controlled by a central processor. The singal conditioners for various temperature and humidity sensors are designed and experimental results are shown.