• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.428-430
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• 2011

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.768-770
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• 2010

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embeded systems.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.435-442
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• 2018

This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.833-835
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• 2010

The SPARTAN-3E development kit is equipped with an FPGA which holds 500 thousand logic gates and a bus system platform using MicroBlaze microprocessor system. This kind of embedded systems can be used to gather information from sensor nodes and send over to the main server periodically through the network gateway, using the microprocessor-based embedded system, so that edlers living alone under sensor coverage can send their moving information and can be applied to get help in the event of emergency situations. In this paper, we designed a simple embedded system based on a CPU and flash memories using such FPGAs which can be used to monitor those elderlies living alone. The developed hardware system can be directly combined with the web-based elders-living-alone monitoring system, making the system more efficient.

• Journal of Korea Multimedia Society
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• v.15 no.7
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• pp.920-930
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• 2012

In this paper, we designed and built a wired temperature controller system which is based on ASIC for a wireless temperature controller system based on FPGA. FPGA devices and wireless controller systems are growing quickly especially for industrial systems for sensing temperature and humidity. FPGA can set up a desired system and a CPU, and directly set up or change a peripheral device based on an IP quickly for an affordable price. This wireless system is easy to install in the field where there are lots of changes and the system is complex. It also has advantages for maintenance. In this study, we are using a 32 bit RISC CPU based on MicroBlaze, with a touch interface, peripheral device, and porting the embedded Linux. Also, we added wireless communication using ZigBee. With this system we provide remote monitoring and control through the web by adding a web server. Compared to the original system, we say not only a performance improvement, but also more efficient development and cheaper costs. In this study, we focused especially on building a better development environment and a more effective user interface.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.2
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• pp.278-287
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• 2011

NMEA 2000 protocol known as IEC 61162-3 of Multi-talker, Multi-listener and Plug and Play network communication has been adopted as standard network for SOLAS(Safety of Life at Sea) ship by IMO. This paper focuses on the implementation of FPGA and MicroBlaze for NMEA 2000 based gateway, which is able to convert NMEA 2000 protocol into various types of network protocol such as Ethernet, UART and USB using Vertex4-based ML401 board. Each communication module and the stack of NMEA 2000 are mounted on FPGA. To be able to receive each communication data, ML401 board is configured to handle required communication speed. PC based NMEA 2000 monitoring program is developed to verify that data on different networks are correctly converted each other in real time.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.10
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• pp.1923-1928
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• 2010

The IEC 61850 protocol proposed for the interoperability between IEDs(intelligent electronic devices) adopts the prioritized switched ethernet as its communication channel because substation bus is utilized to exchange both real-time and non real-time messages. The prioritized switched ethernet uses IEEE 802.1Q/p QoS(Quality of Service) in addition to IEEE 802.3 ethernet to enhance the real-time characteristics. However, IEEE 802.1Q/p QoS has priority-blocking problem that occurs when higher-priority frame transmission request during lower-priority frame transmission. To resolve this problem, this paper proposes P(Preemptive)-Ethernet. P-Ethernet uses the modified IEEE 802.1Q/p frame format and new priority preemption mechanism. This paper also implements P-Ethernet controller using FPGA (Virtex-4) and MicroBlaze processor. From the implementation results, P-Ethernet controller shows a improved latency and jitter of transmission period compare to the normal ethernet controller.

• Journal of Advanced Navigation Technology
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• v.17 no.1
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• pp.69-79
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• 2013

In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.5
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• pp.27-37
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• 2012

Even thought the firefighters have to hurry to the scene to extinguish the blaze, the fire engines could not rushed out due to the worst of traffic condition. Traffic signal control is one of the most important methods to minimize the fire engines's travel time. The focus of this paper is to develop a traffic control strategy, which is emergency vehicle preemption algorithm considering pedestrian in order to reduce travel time of emergency vehicle. This algorithm also includes recovering strategy after preemption signal to minimize the other vehicle's delay. In order to estimate the effectiveness of traffic control, traffic simulation was performed using VISSIM micro simulation tool for two different kinds of networks, which were non-coordinated corridor and coordinated corridor. The differences of travel time and average delay between emergency vehicle and ordinary vehicle were respectively estimated under pre-existed pretimed signal and preemption traffic control at two respective networks. The results of the simulation for the emergency vehicle, travel time was reduced to 36.8~43.3% under "Add or Subtract" method whereas it was reduced to 30.7~46.0% under "Dwell" method. In addition, in non-coordinated corridor case of ordinary vehicle, average control delay of "Dwell" method was increased 33.5% whereas it grew 0.5% under coordinated corridor. And "Add or Subtract" method was confirmed that average control delay of ordinary vehicle was increased 0.7% under non-coordinated corridor whereas it swelled 4.5% under coordinated corridor.