• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 A
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• pp.278-281
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• 1995

In this paper, a instantaneous speed measurement methode using a three phase sinusoidal taco-generator is described and it's simulations are developed. The proposed methode can easily detect the motor speed by using that the output voltage of taco-generator is propotion to the motor speed. Because the proposed methode consists of some calculation, the proposed system can be implemented with analog devices or micro processor conveniently. From the simulation resualts, the proposed measurement methode can acculately detect the real motor speed over wide range.

• 품질경영학회지
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• 제14권2호
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• pp.9-14
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• 1986

The primary purpose of this paper is to make the management of small business aware of the potential and further, to assist their decision on purchasing and applying the personal computers to their business problems. With emphasis on the step by step expansion various computer hardware systems are reviewed, compared and evaluated in its price, micro-processor, memory size, software availability, etc. Using the concept of incremental costs, a method to evaluate software packages is developed. By this method the optimal system can be determined.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 추계학술대회 논문집
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• pp.613-614
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• 2006

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.34-36
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• 2002

This paper addresses an elevator position control scheme in unified control system. Conventional systems have employed independent micro-processors for speed, car, and group control respectively and the car controller generates a velocity command by combining the time-based and distance-based velocity pattern. In this scheme, it is inevitable that an elevator creeps in the vicinity of target floor, or stops abruptly. The proposed control system employs only one high-performance micro-processor, which can execute the car and group control as well as the speed control. It simply generates the desired position trajectory based on time and on-line corrects a velocity pattern to make the position error be zero. Experimental results show the feasibility of the proposed control scheme.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.337-337
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• 2000

This paper describes a Chuck System developed for scaling PDP gas hole on PDP panel glass. There are lots of constraints for designing Chuck System: high temperature, high vacuum, precious motor control etc. A such constraints was considered by design of structure and by selecting of parts and material for Chuck System. The Chuck System was manufactured and assembled after the design process. It was applied on the PDP process unit. For sealing POP hole, precious control of a step motor was important in this system. For this experiment, a step motor, motor driver and micro controller(80196KC) were used.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.834-837
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• 1993

This paper describes the implementation of an autonomous fuzzy logic controller. The controller is endowed with basic control principles and learning constructs which enable it to autonomously modify its control policy based on system performance. The controller lies dormant when system response is satisfactory but if rapidly initiates adaptation in real time when adverse performance is observed. The autonomous fuzzy controller is implemented on an Intel MCS-51 series micro-controller board using an inexpensive 8-bit Intel 8031 processor. The 11.06 MHz micro-controller operates at a rate exceeding 200 "global" look-up table reinforcements per second. This is important when developing practical on-line adaptive controllers for fast systems. It is also significant because an initial controller look-up table could be incorrect or non-existent. The relatively high learning rate enables the controller to learn to control a system even while it is controlling it.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• 대한전자공학회논문지
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• 제24권3호
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• pp.425-432
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• 1987

The microprogram is the key technology of the implementation of the processor's control unit. But the coding and testing it is the most tedious process in the developing a new computer system. We developed the conversational micro architecture simulator(C-MAS) in order to use it as a microprogram development tool and a run time analyzer of the microprogram. We discuss the hardware description language(HDL) for a smulation, the design constraints of the C-MAS, and the user interface of it in this paper. We used the C language as the description language, and developed it on the berkeley UNIX4.2.

• 정보과학회 논문지
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• 제44권2호
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• pp.115-123
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• 2017

메시지 처리기란 다양한 클라이언트로부터 오는 메시지를 받아 처리하는 서버 소프트웨어이며, 메시지의 종류에 따라 마감기한 이내에 처리해야 하는 실시간 메시지와 비실시간 메시지를 처리한다. 최근 마이크로프로세서 기술의 발전과 리눅스의 빠른 보급에 따라 메시지 처리기는 멀티코어 기반의 리눅스 서버에서 구현되고 있으며, 멀티코어 환경에서는 코어를 효율적으로 사용해야 시스템의 성능을 극대화 시킬 수 있다. 멀티코어를 효율적으로 사용하기 위한 다양한 실시간 스케줄러가 제안되어 있지만, 많은 연구들이 이론적 분석이나 시뮬레이션에 국한되어 있고, 리눅스를 위해 제안된 일부 알고리즘들도 커널을 수정하거나 특정 커널 버전에서만 동작된다는 단점이 있다. 본 논문에서는 멀티코어 환경에서 쓰레드를 사용자 수준에서 코어에 직접 매핑하는 리눅스 기반 메시지 처리기의 구조를 제안한다. 구현된 메시지 처리기에서는 기존의 RM(Rate Monotonic) 알고리즘을 수정하여 사용하였고, 특정 코어에 최대한 실시간 메시지를 몰아서 처리하도록 First fit 기반의 빈패킹(Bin-Packing) 알고리즘을 사용하여, 실시간 메시지의 위배율을 보장하면서 비실시간 메시지의 응답시간의 지연을 최소화하였다. 성능평가를 위하여 LITMUS 프레임 워크에서 제공하는 2가지 멀티코어 스케줄링 알고리즘(GSN-EDF, P-FP)을 이용하여 메시지 처리기를 구현한 후 제안된 시스템과 비교한 결과, 비실시간 메시지의 응답시간이 2가지 알고리즘 대비 최대 17~18%까지 향상되는 것을 확인하였다.