• Bulletin of the Korean Chemical Society
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• 제34권11호
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• pp.3451-3455
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• 2013

Single-crystalline silicon nanowires (SiNWs) were fabricated by using an electroless metal-assisted etching of bulk silicon wafers with silver nanoparticles obtained by wet electroless deposition. The etching of SiNWs is based on sequential treatment in aqueous solutions of silver nitrate followed by hydrofluoric acid and hydrogen peroxide. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the Si substrate were produced. Free-standing SiNWs were then obtained using ultrasono-method in toluene. Alkyl-derivatized SiNWs were prepared to prevent the aggregation of SiNWs and obtained from the reaction of SiNWs and dodecene via hydrosilylation. Optical characterizations of SiNWs were achieved by FT-IR spectroscopy and indicated that the surface of SiNWs is terminated with hydrogen for fresh SiNWs and with dodecyl group for dodecyl-derivatized SiNWs, respectively. The main structures of dodecyl-derivatized SiNWs are wires and rods and their thicknesses of rods and wire are typically 150-250 and 10-20 nm, respectively. The morphology and chemical state of dodecyl-derivatized SiNWs are characterized by scanning electron microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy.

• 전기화학회지
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• 제16권1호
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• pp.1-8
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• 2013

본 총설에서는 Si 비등방성 식각(anisotropic etching) 공정인 metal-assisted chemical etching(MAC etch 혹은 MACE) 분야 기본 원리, 중요 변수, 그리고 최근 연구 성과들을 정리하였다. 1990년에 최초로 Si 표면에 금속 촉매를 증착한 후 $H_2O_2$/HF 기반 식각을 진행하면 용액 중에서도 비등방성 식각을 통해 다양한 고종횡비(high aspect ratio) 나노구조를 형성할 수 있다는 것이 밝혀 졌다. 고가의 진공기반 장비가 필요한 건식 식각에 비해, 습식 식각을 통해서도 상대적으로 간편하고 경제적으로 종횡비가 큰 Si 마이크로/나노 구조를 만들 수 있게 되었다. 초기 연구들을 통해 MAC etch중 산화제가 촉매에 의해 환원되고, 촉매/Si 계면 근처의 Si 원자들이 선택적으로 식각/용해되어 수직 방향으로 촉매가 Si 기판을 파고 들어가며 비등방성 식각이 발생함이 밝혀졌다. MAC etch에 영향을 미치는 중요 변수로는 금속 촉매의 종류 및 모양, 식각액의 조성, Si기판의 도핑 농도이다. 또한 본 총설은 MAC etch에 의해 형성된 Si 나노 구조를 이용한 태양전지, 수소 연료, 리튬 이온 전지 등의 응용 분야를 다루었다.

• Transactions on Electrical and Electronic Materials
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• 제10권5호
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• pp.147-151
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• 2009

For integrated passive device (IPD) applications, we have successfully developed and characterized metalinsulator-metal (MIM) capacitors with 2000 $\AA$ plasma-enhanced chemical vapor deposition (PECVD) silicon nitride which are deposited with the $SiH_4/NH_3$ gas mixing rate, working pressure, and RF power of PECVD at $250^{\circ}C$. Five PECVD process parameters are designed to lower the refractive index and lower the deposition rate of $Si_3N_4$ films for the high breakdown electric field. For the PECVD process condition of gas mixing rate (0.957), working pressure (0.9 Torr), and RF power (60 W), the atomic force microscopy (AFM) root mean square (RMS) value of about 2000 $\AA$ $Si_3N_4$ on the bottom metal is lowest at 0.862 nm and the breakdown electric field is highest at about 8.0 MV/cm with a capacitance density of 326.5 pF/$mm^2$. A pretreatment of metal electrodes is proposed, which can reduce the peeling of nitride in the harsh test environment of heat, pressure, and humidity.

• Bulletin of the Korean Chemical Society
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• 제13권5호
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• pp.542-546
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• 1992

New silicon-monosubstituted (${\eta}^4$-2,3,4,5-tetraphenyl-1-silacyclopentadiene)transi tion metal complexes are described. The new (silole-transition metal complex)Fe$(CO)_3$ was obtained from the reaction of silole-tansition metal complex and Fe$(CO)_5$. We have determined the crystal structure of (${\eta}^4$-exo-cyclopentadienyldicarbonyliron-endo-1-meth yl-2,3,4,5-tetraphenyl-1-silacyclopentadienyl)tric arbonyliron by using graphitemonochromated Mo-$K_{\alpha}radiation. The compound was crystallized in the monoclinic space group $P2_1$/c with a = 8.925(1), b = 18.689(3), c = 19.930(3) ${\AA}$, and ${\beta}$ = 102.02$(1)^{\circ}$. The iron moiety CpFe$(CO)_2$ on silicon is in an axal position. The (silole-transition metal complex) Fe$(CO)_3$ was also prepared through the reaction of (${\eta}^4$-1-chloro-2,3,4,5-tetraphenylsilacyclopentadiene) Fe$(CO)_3$ and metal complex nucleophile. The structure configuration was studied by conventional spectroscopy.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.88.1-88.1
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• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.

• 융합정보논문지
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• 제9권5호
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• pp.117-124
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• 2019

본 논문에서는 AMOLED 디스플레이 구동회로로 사용되는 박막트랜지스터의 구성요소 중에서 반도제 물질 제조의 최근 동향에 대해 논한다. 트랜지스터에 적용을 위해 특성이 좋은 반도체 막을 얻는 방법으로 비정질 실리콘을 다결정 실리콘으로 변화시켜야 하는데 레이저와 열처리 방법이 있으며, 레이저를 이용한 기술에는 SLS(Sequential Lateral Solidification), ELA(Excimer Laser Annealing), TDX(Thin-beam Directional Crystallization), 열처리 기술에는 SPC(Solid Phase Crystallization), SGS(Super Grain Silicon), MIC(Metal Induced Crystallization), FALC(Field Aided Lateral Crystallization)가 대표적이며, 이들에 대해 상세히 설명한다. 본 연구실에서 연구중인 레이저 결정화 기술의 대형 AMOLED 디스플레이 제작을 위한 연구 내용도 다룬다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.313-313
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• 2013

For high-performance TFT (Thin film transistor), poly-crystalline semiconductor thin film with low resistivity and high hall carrier mobility is necessary. But, conventional SPC (Solid phase crystallization) process has disadvantages in fabrication such as long annealing time in high temperature or using very expensive Excimer laser. On the contrary, MIC (Metal-induced crystallization) process enables semiconductor thin film crystallization at lower temperature in short annealing time. But, it has been known that the poly-crystalline semiconductor thin film fabricated by MIC methods, has low hall mobility due to the residual metals after crystallization process. In this study, Ni metal was shallow implanted using PIII&D (Plasma Immersion Ion Implantation & Deposition) technique instead of depositing Ni layer to reduce the Ni contamination after annealing. In addition, the effect of external magnetic field during annealing was studied to enhance the amorphous silicon thin film crystallization process. Various thin film analytical techniques such as XRD (X-Ray Diffraction), Raman spectroscopy, and XPS (X-ray Photoelectron Spectroscopy), Hall mobility measurement system were used to investigate the structure and composition of silicon thin film samples.

• 한국기계가공학회지
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• 제21권2호
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• pp.109-115
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• 2022

The demand for metal 3D printing technology is increasing in various industries. The materials commonly used for metal 3D printing include aluminum alloys, titanium alloys, and stainless steel. In particular, for applications in the aviation and defense industry, aluminum alloy 3D printing parts are being produced. To improve the corrosion resistance in the 3D printed aluminum alloy outputs, a post-treatment process, such as chromate coating, should be applied. However, powdered materials, such as AlSi7Mg and AlSi10Mg, used for 3D printing, have a high silicon content; therefore, a suitable pretreatment is required for chromate coating. In the desmut step of the pretreatment process, the chromate coating can be formed only when a smut composed of silicon compounds or oxides is effectively removed. In this study, suitable desmut solutions for 3D printed AlSi7Mg and AlSi10Mg materials with high silicon contents were presented, and the chromate coating properties were studied accordingly. The smut removal effect was confirmed using an aqueous desmut solution composed of sulfuric, nitric, and hydrofluoric acids. Thus, a chromate coating was successfully formed. The surfaces of the aluminum alloys after desmut and chromate coating were analyzed using SEM and EDS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• 한국분말야금학회:학술대회논문집
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• 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part2
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• pp.850-850
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• 2006