• ETRI Journal
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• 제46권3호
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• pp.550-563
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• 2024

A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.

• 반도체디스플레이기술학회지
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• 제18권1호
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• pp.32-37
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• 2019

Titanium dioxide ($TiO_2$) is a promising dielectric material in the semiconductor industry for its high dielectric constant. However, for utilization on Si substrate, $TiO_2$ film meets with a difficulty due to the large leakage currents caused by its small conduction band energy offset from Si substrate. In this study, we propose an in-situ plasma oxidation process in plasma-enhanced atomic layer deposition (PE-ALD) system to form an oxide barrier layer which can reduce the leakage currents from Si substrate to $TiO_2$ film. $TiO_2$ film depositions were followed by the plasma oxidation process using tetrakis(dimethylamino)titanium (TDMAT) as a Ti precursor. In our result, $SiO_2$ layer was successfully introduced by the plasma oxidation process and was used as a barrier layer between the Si substrate and $TiO_2$ film. Metal-oxide-semiconductor ($TiN/TiO_2/P-type$ Si substrate) capacitor with plasma oxidation barrier layer showed improved C-V and I-V characteristics compared to that without the plasma oxidation barrier layer.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.25-35
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• 2000

금속-산화막-반도체 소자의 산화막에 존재하는 느린 준위에 의한 전류반응 특성을 양방향 전류-전압 측정기술을 적용하여 분석하였다. 게이트 바이어스에 따라 나타나는 충전 및 방전시의 순간전류를 유지시간, 지연시간, 전자주입 방향 및 전자주입량, 그리고 전자 주입후 상온 방치시간의 함수로서 조사하였다. 느린 준위의 전하교환에 따른 전류 성분을 게이트 전압에 따라 실리콘 내 캐리어의 이동에 의해 나타나는 변위전류와 분리하여 해석하였다. 충전 및 방전시 나타나는 전하교환 전류는 산화막내 정전하 밀도뿐만 아니라 계면준위 밀도에도 크게 의존이 되며, 본 연구에서는 느린 준위의 전하교환 메카니즘을 제시하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.318-321
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• 2000

We showed that the change of Ar to $N_2$flow during the TiN deposition by the reactive sputtering decides the crystallinity of LPCVD W, as well as the electrical properties of the W-TiN/SiO$_2$Si capacitor. In particular, the threshold voltage can be controlled by the Ar to $N_2$ratio. As compared to the results obtained from the LPCVD W/SiO$_2$/Si MOS capacitor, the insertion of approximately 50 nm TiN film effectively prohibits the fluorine diffusion during the deposition and annealing of W films, resulting in negligible leakage currents at the low electric fields.

• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• Journal of information and communication convergence engineering
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• 제13권3호
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• pp.189-196
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• 2015

In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.300-300
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• 2011

Si oxidation is a key process in developing silicon devices, such as highly integrated metal-oxide-semiconductor (MOS) transistors and antireflection-coating (ARC) on solar cell substrate. Many experimental and theoritical studies have been carried out for elucidating oxidation processes and adsorption structure using ab initio total energy and electronic structure calcultaions. However, the initial oxidation processes at step edge on vicinal Si surface have not been studied using the ReaxFF reactive force field. In this work, strucutural change, charge distribution of oxidized Si throughout the depth from Si surface were observed during oxidation processes on vicinal Si(001) surface inclined by $10.5^{\circ}$ of miscut angle toward [100]. Adsorption energys of step edge and flat terrace were calculated to compare the oxidation reaction at step edge and flat terrace on Si surface.

• ETRI Journal
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• 제32권1호
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• pp.68-72
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• 2010

The coupling between the transverse and longitudinal components of the channel electron motion in NMOS devices leads to a reduction in the barrier height. Therefore, this study theoretically investigates the effects of the in-plane velocity of channel electrons on the capacitance-voltage characteristics of nano NMOS devices under inversion bias. Numerical calculation via a self-consistent solution to the coupled Schrodinger equation and Poisson equation is used in the investigation. The results demonstrate that such a coupling largely affects capacitance-voltage characteristic when the in-plane velocity of channel electrons is high. The ballistic transport ensures a high in-plane momentum. It suggests that such a coupling should be considered in the quantum capacitance-voltage modeling in ballistic transport devices.

• 한국전기전자재료학회논문지
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• 제15권1호
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.