• Title/Summary/Keyword: Metal oxide material

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The Stability Appraisement on Cultural Property Material with the Replacing Fumigation Gas of Methyl Bromide (Methyl Bromide를 대체하는 훈증 가스의 문화재 재질 안정성 평가)

  • Kang, Dai-Ill
    • Journal of Conservation Science
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    • v.25 no.3
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    • pp.283-291
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    • 2009
  • Methyl Bromide that was used as fumigation gas turned out to be the substance of destroying the ozone layer. For that reason, at the Montreal Protocol in 1987 the use of methyl bromide was forbidden starting 2005 in the advanced country. Also according to the 2007 Bali Protocolly methyl bromide is expected to be forbidden and therefore the purpose of this study is to find out the effects of substitution fumigation gas (Ethylene Oxide+HFC 134a, Methyl Iodide, Cyanogen and Argon) on the metal(silver, copper and iron), wood(oregon pine), pigment(yellow, red, blue, white and black), textile(hemp, ramie, jute, silk1 and silk2 / indigo, safflower and cork) and paper. After the fumigation test, ethylene oxide+HFC 134a did not have changes in the weight and color of the material itself before and after the experiment. On exterior alteration, color change occurred partly on paper and metal. Also, in most materials color change extent was 0.5 to 1.5 on the average and showed scanty difference. The materials after the fumigation test with methyl iodide did not show weight changes after the test. However, color changes more than 1.0 was shown in most of the materials especially in dyed textile material. In blue pigment, the discoloration on the surface could be seen by naked eyes. Fumigation test with cyanogen gas did not show weight changes and discoloration is more than 1.5 before and after the test. The weight changes of test materials with the argon gas was decreased about 3 to 6%. It can be observed that discoloration on paper was generated. Color changes can be seen on jute dyed with safflower and cork for two weeks with argon gas and the extent was 6.3 and 6.0.

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Fabrication of Coated Conductor by Continuous PVD Methods (연속 공정 PVD 방법에 의한 Coated Conductor 제조)

  • Ko, Rock-Kil;Chung, Jun-Ki;Kim, Ho-Sup;Ha, Hong-Soo;Shi, Dongqi;Song, Kyu-Jeong;Park, Chan;Yoo, Sang-Im;Moon, Seung-Hyun;Kim, Young-Cheol
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.11
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    • pp.1241-1245
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    • 2004
  • Continuous physical vapor deposition (PVD) method is one of many processes to fabricate long length coated conductor which is required for successful large-scale application of superconducting power devices. Three film deposition systems (pulsed laser deposition, sputtering, and evaporation) equipped with reel-to-reel(R2R) metal tape moving apparatus were installed and used to deposit multi-layer oxide thin films. Both RABiTS and IBAD texture templates are used. IBAD template consists of CeO$_2$(PLD)/YSZ(IBAD) on stainless steel(SS) metal tape, and RABiTS template has the structure of CeO$_2$/YSZ/Y$_2$O$_3$ which was continuously deposited on Ni-alloy tape using R$_2$R evaporation and DC reactive sputtering in a deposition system designed to do both processes. 0.4 m-long coated conductor with Ic(77 K) of 34 A/cm was fabricated using RABiTS template. 0.5 m and 1.1 m-long coated conductor with Ic(77 K) of 41 A/cm and 26 A/cm were fabricated using IBAD template.

Hole Selective Contacts: A Brief Overview

  • Sanyal, Simpy;Dutta, Subhajit;Ju, Minkyu;Mallem, Kumar;Panchanan, Swagata;Cho, Eun-chel;Cho, Young Hyun;Yi, Junsin
    • Current Photovoltaic Research
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    • v.7 no.1
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    • pp.9-14
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    • 2019
  • Carrier selective solar cell structure has allured curiosity of photovoltaic researchers due to the use of wide band gap transition metal oxide (TMO). Distinctive p/n-type character, broad range of work functions (2 to 7 eV) and risk free fabrication of TMO has evolved new concept of heterojunction intrinsic thin layer (HIT) solar cell employing carrier selective layers such as $MoO_x$, $WO_x$, $V_2O_5$ and $TiO_2$ replacing the doped a-Si layers on either front side or back side. The p/n-doped hydrogenated amorphous silicon (a-Si:H) layers are deposited by Plasma-Enhanced Chemical Vapor Deposition (PECVD), which includes the flammable and toxic boron/phosphorous gas precursors. Due to this, carrier selective TMO is gaining popularity as analternative risk-free material in place of conventional a-Si:H. In this work hole selective materials such as $MoO_x$, $WO_x$ and $V_2O_5$has been investigated. Recently $MoO_x$, $WO_x$ & $V_2O_5$ hetero-structures showed conversion efficiency of 22.5%, 12.6% & 15.7% respectively at temperature below $200^{\circ}C$. In this work a concise review on few important aspects of the hole selective material solar cell such as historical developments, device structure, fabrication, factors effecting cell performance and dependency on temperature has been reported.

A Study on the Growth Temperature of Atomic Layer Deposition for Photocurrent of ZnO-Based Transparent Flexible Ultraviolet Photodetector (원자층 증착법의 성장온도에 따른 산화아연 기반 투명 유연 자외선 검출기의 광전류에 대한 연구)

  • Choi, Jongyun;Lee, Gun-Woo;Na, Young-Chae;Kim, Jeong-Hyeon;Lee, Jae-Eun;Choi, Ji-Hyeok;Lee, Sung-Nam
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.35 no.1
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    • pp.80-85
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    • 2022
  • ZnO-based transparent conductive films have been widely studied to achieve high performance optoelectronic devices such as next generation flexible and transparent display systems. In order to achieve a transparent flexible ZnO-based device, a low temperature growth technique using a flexible polymer substrate is required. In this work, high quality flexible ZnO films were grown on colorless polyimide substrate using atomic layer deposition (ALD). Transparent ZnO films grown from 80 to 200℃ were fabricated with a metal-semiconductor-metal structure photodetectors (PDs). As the growth temperature of ZnO film increases, the photocurrent of UV PDs increases, while the sensitivity of that decreases. In addition, it is found that the response times of the PDs become shorter as the growth temperature increases. Based on these results, we suggest that high-quality ZnO film can be grown below 200℃ in an atomic layer deposition system, and can be applied to transparent and flexible UV PDs with very fast response time and high photocurrent.

Impact of Remanent Polarization and Coercive Field on Threshold Voltage and Drain-Induced Barrier Lowering in NCFET (negative capacitance FET) (NCFET (negative capacitance FET)에서 잔류분극과 항전계가 문턱전압과 드레인 유도장벽 감소에 미치는 영향)

  • Hakkee Jung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.1
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    • pp.48-55
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    • 2024
  • The changes in threshold voltage and DIBL were investigated for changes in remanent polarization Pr and coercive field Ec, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when Pr decreases and Ec increases, and the threshold voltage is also maintained constant when the Pr/Ec is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to Pr/Ec, so the DIBL greatly changes for Pr/Ec. In other words, when Pr/Ec=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO2 thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the Pr/Ec is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the Pr and Ec of ferroelectric.

Design of the High Brightness LED Driver IC with Enhanced the Output Current Control Function (출력전류 제어 기능이 향상된 고휘도 LED 구동 IC 설계)

  • Song, Ki-Nam;Han, Seok-Bung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.8
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    • pp.593-600
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    • 2010
  • In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

In-situ monitoring of oxidation states of vanadium with ambient pressure XPS

  • Kim, Geonhwa;Yoon, Joonseok;Yang, Hyukjun;Lim, Hojoon;Lee, Hyungcheol;Jeong, Changkil;Yun, Hyungjoong;Jeong, Beomgyun;Ethan, Crumlin;Lee, Juhan;Ju, Honglyoul;Mun, Bongjin Simon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.125.2-125.2
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    • 2015
  • The evolution of oxidation states of vanadium is monitored with ambient pressure X-ray photoemission spectroscopy. As the pressure of oxygen gas and surface temperature change, the formations of various oxidation states of vanadium are observed on the surface. Under 100mTorr of the oxygen gas pressure and 523K of sample temperature, VO2 and V2O5 are formed on the surface. The temperature-dependent resistance measurement on grown sample shows a clear metal-insulator transition near 350K. In addition, the measurement of Raman spectroscopy displays the structural change from monoclinic to rutile structures across the phase transition temperature.

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A Study on Module Design and Performance of Polymer Arrester (폴리머 피뢰기의 모듈 설계 및 성능에 관한 연구)

  • Cho, Han-Goo;Chun, Jong-Uk;Kang, Yeong-Kil
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05e
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    • pp.108-111
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    • 2003
  • The main objective of this paper is to module design and pressure relief test a new type of polymer gapless surge arrester for power distribution line. Metal oxide surge arrester for most electric power system applications, power distribution line and electric train are now being used extensively to protect overvoltage due to lightning. Surge arresters with porcelain housing must not have explosive breakage of the housing to minimize damage to other equipment when subjected to internal high short circuit current. When breakdown of gapless elements in a surge arrester occurs due to flashover, fault short current flows through the arrester and internal pressure of the arrester rises. The pressure rise can usually be limited by fitting a pressure relief diaphragm and transferring the arc from the inside to the outside of the housing. However, there is possibility of porcelain fragmentation caused by the thermal shock, pressure rise, etc. Non-fragmenting of the housing is the most desired way to prevent damage to other equipment. The pressure change which is occurred by flashover become discharge energy. This discharge energy raises to damage arrester housing and arrester housing is dispersed as small fragment. Therefore, the pressure relief design is requested to obstruct housing dispersion.

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Current Sensing Circuit of MOSFET Switch for Boost Converter (부스터 변환기를 위한 MOSFET 스위치 전류 감지 회로)

  • Min, Jun-Sik;No, Bo-Mi;Kim, Eui-Jin;Lee, Chan-Soo;Kim, Yeong-Seuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.9
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    • pp.667-670
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    • 2010
  • In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

Extraction of Threshold Voltage for Junctionless Double Gate MOSFET (무접합 이중 게이트 MOSFET에서 문턱전압 추출)

  • Jung, Hak Kee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.3
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    • pp.146-151
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    • 2018
  • In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.