• Transactions on Electrical and Electronic Materials
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• v.5 no.5
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.407.1-407.1
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• 2016

Electrochromism is defined as a phenomenon which involves persistently repeated change of optical properties between bleached state and colored state by simultaneous injection of electrons and ions, sufficient to induce an electrochemical redox process. Due to this feature, considerable progress has been made in the synthesis of electrochromic (EC) materials, improvements of EC properties in EC devices such as light shutter, smart window and variable reflectance mirrors etc. Among the variable EC materials, solid-state inorganics in particular, metal oxide semiconducting materials such as nickel oxide (NiO) have been investigated extensively. The NiO that is an anodic EC material is of special interest because of high color contrast ratio, large dynamic range and low material cost. The high performance EC devices should present the use of standard industrial production techniques to produce films with high coloration efficiency, rapid switching speed and robust reversibility. Generally, the color contrast and the optical switching speed increase drastically if high surface area is used. The structure of porous thin film provides a specific surface area and can facilitate a very short response time of the reaction between the surface and ions. The large variety of methods has been used to prepare the porous NiO thin films such as sol-gel process, chemical bath deposition and sputtering. Few studies have been reported on NiO thin films made by using sol-gel method. However, compared with dry process, wet processes that have the questions of the durability and the vestige of bleached state color limit the thin films practical use, especially when prepared by sol-gel method. In this study, we synthesis the porous NiO thin films on the fluorine doped tin oxide (FTO) glass by using sputtering and anodizing method. Also we compared electrical and optical properties of NiO thin films prepared by sol gel. The porous structure is promised to be helpful to the properties enhancement of the EC devices.

• Korean Journal of Materials Research
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• v.20 no.8
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.429-429
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• 2008

Li$[Ni_{1/2}Co_{1/2}]O_2$ powder were synthesized from co-precipitation spherical metal oxide, $[Ni_{1/2}Co_{1/2}](OH)_2$. The preparation of metal hydroxide was significantly dependent on synthetic conditions, such as pH, amount of chelating agent, stirring speed, etc. The optimized condition resulted in $[Ni_{1/2}Co_{1/2}](OH)_2$, of which the particle size distribution was uniform and the particle shape was spherical, as observed by scanning electron microscopy. Calcination of the uniform metal hydroxide with LiOH at higher temperature led to a well-ordered layer-structured Li$[Ni_{1/2}Co_{1/2}]O_2$, as confirmed by X-ray diffraction pattern. Also these materials have ${\alpha}-NaFeO_2$ ($R\bar{3}m$) structure. Due to the homogeneity of the metal hydroxide, $[Ni_{1/2}Co_{1/2}](OH)_2$, the final product, Li$[Ni_{1/2}Co_{1/2}]O_2$, was also significantly uniform, i.e., the average particle size was of about 10 to 15 ${\mu}m$ in diameter and the distribution was relatively narrow. As a result, the corresponding tap-density was also high approximately 2.41 $gcm^{-3}$, of which the value is comparable to that of commercialized $LiCoO_2$.

• Electrical & Electronic Materials
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• v.9 no.8
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• pp.789-798
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• 1996

The double nitride layer Metal Nitride Oxide Semiconductor(MNOS) structures were fabricated by variating both gas ratio and nitride thickness, and by duplicating nitride deposited and one nitride layer MNOS structure to improve nonvolatile memory characteristics of MNOS structures by Low Pressure Chemical Vapor Deposition(LPCVD) method. The nonvolatile memory characteristics of write-in, erase, memory retention and degradation of Bias Temperature Stress(BTS) were investigated by the homemade automatic .DELTA. $V_{FB}$ measuring system. In the trap density double nitride layer structures were higher by 0.85*10$^{16}$ $m^{-2}$ than one nitride layer structure, and the AVFB with oxide field was linearly increased. However, one nitride layer structure was linearly increased and saturated above 9.07*10$^{8}$ V/m in oxide field. In the erase behavior, the hole injection from silicon instead of the trapped electron emission was observed, and also it was highly dependent upon the pulse amplitude and the pulse width. In the memory retentivity, double nitrite layer structures were superior to one nitride layer structure, and the decay rate of the trapped electron with increasing temperature was low. At increasing the number on BTS, the variance of AVFB of the double nitride layer structures was smaller than that of one nitride layer structure, and the trapped electron retention rate was high. In this paper, the double nitride layer structures were turned out to be useful in improving the nonvolatile memory characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.207.1-207.1
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• 2014

High-mobility and two dimensional conduction at the interface between two band insulators, LaAlO3 (LAO) and SrTiO3 (STO), have attracted considerable research interest for both applications and fundamental understanding. Several groups have reported the photoconductivity of LAO/STO, which give us lots of potential development of optoelectronic applications using the oxide interface. Recently, a giant photo response of Pd nano particles/LAO/STO is observed in UV illumination compared with LAO/STO sample. These phenomena have been suggested that the correlation between the interface and the surface states significantly affect local charge modification and resulting electrical transport. Water and gas adsorption/desorption can alter the band alignment and surface workfunction. Therefore, characterizing and manipulating the electric charges in these materials (electrons and ions) are crucial for investigating the physics of metal oxide. Proposed mechanism do not well explain the experimental data in various ambient and there has been no quantitative work to confirm these mechanism. Here, we have investigated UV photo response in various ambient by performing transport and Kelvin probe force microscopy measurements simultaneously. We found that Pd nano particles on LAO can form Schottky contact, it cause interface carrier density and characteristics of persistence photo conductance depending on gas environment. Our studies will help to improve our understanding on the intriguing physical properties providing an important role in many enhanced light sensing and gas sensing applications as a catalytic material in different kinds of metal oxide systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.96-99
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• 2014

In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.317-322
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• 2015

The metal oxide varistor (MOV) is a major component of the surge protection devices (SPDs) currently in use. The device is judged to be faulty when fatigue caused by the continuous inflow of lightning accumulates and reaches the damage limit. In many cases, induced lightning resulting from lightning strikes flows in to the device several times per second in succession. Therefore, the frequency or the rate at which the SPD is actually exposed to stress, called a surge, is outside the range of human perception. For this reason, the protective device should be replaced if it actually approaches the end of its life even though it is not faulty at present, currently no basis exists for making the judgment of remaining lifetime. Up to now, the life of an MOV has been predicted solely based on the number of inflow surges, irrespective of the magnitude of the surge current or the amount of energy that has flowed through the device. In this study, nonlinear data that shows the damage to an MOV depending on the count of surge and the amount of input current were collected through a high-voltage test. Then, a failure prediction algorithm was proposed by preparing a look-up table using the results of the test. The proposed method was experimentally verified using an impulse surge generator

• Transactions on Electrical and Electronic Materials
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• v.12 no.5
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• pp.175-188
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• 2011

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.