• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of Information Display
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• 제13권2호
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• 한국재료학회지
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• 제16권3호
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• pp.151-156
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• 2006

A method for fabrication of nano-scale GaN structure by inductively coupled plasma etching is proposed, exploiting a thermal dewetting of Pt thin film as an etch mask. The nano-scale Pt metal islands were formed by the dewetting of 2-dimensional film on $SiO_2$ dielectric materials during rapid thermal annealing process. For the case of 30 nm thick Pt films, pattern formation and dewetting was initiated at temperatures greater $600^{\circ}C$. Controlling the annealing temperature and time as well as the thickness of the Pt metal film affected the size and density of Pt islands. The activation energy for the formation of Pt metal island was calculated to be 23.2 KJ/mole. The islands show good resistance to dry etching by a $CF_4$ based plasma for dielectric etching indicating that the metal islands produced by dewetting are suitable for use as an etch mask in the fabrication of nano-scale structures.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2011년도 춘계학술대회 및 Fine pattern PCB 표면 처리 기술 워크샵
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• pp.115-115
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• 2011

고성능 금속 커패시터 개발을 목적으로 aluminum film에 균일한 etch fit를 형성하는 연구를 진행하였다. Etch mask로 PI를 사용하여 Aluminum film에 균일한 형태의 etch fit를 형성하였다. 균일하게 에칭 된 aluminum film들은 capacitance를 측정하여 에칭 조건에 따른 capacitance 변화를 확인하였다.

• 한국표면공학회지
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• 제46권3호
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• pp.99-104
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• 2013

The simple and cost-effective microfabrication method of photosensitive glass (PSG) using metal patterning and blank exposure was proposed. Conventional photolithography for micromachining of PSG needs a costly quartz mask which has high transmittance as an optical property. However, in this study the process was improved through the combination of micro-patterned Ti thin film and blank UV exposure without quartz mask. The effect of UV exposure time as well as the DHF etching condition was investigated. UV exposure test was performed within the range from 3 min to 9 min. The color and etch result of PSG exposed for 5 min were the most clear and effective to etch more precisely, respectively. The etching results of PSG in diluted hydrofluoric acid (DHF) with a concentration of 5, 10, 15 vol% were compared. The effect on the side etch was insignificant while the etch rate was proportional as the concentration increased. 10 vol% DHF results not only high etch rate of 75 ${\mu}m/min$ also lower side etch value after PSG etching. This method facilitates the microfabrication of PSG with various patterns and high aspect ratio for applying to advanced applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.642-642
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• 2013

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as high electron mobility, high thermal conductivity and optical transparency. Especially, chemical vapor deposition (CVD) grown graphene has been used as a promising material for high quality and large-scale graphene film. Unfortunately, although CVD-grown graphene has strong advantages, application of the CVD-grown graphene is limited due to ineffective transfer process that delivers the graphene onto a desired substrate by using polymer support layer such as PMMA(polymethyl methacrylate). The transferred CVD-grown graphene has serious drawback due to remaining polymeric residues generated during transfer process, which induces the poor physical and electrical characteristics by a p-doping effect and impurity scattering. To solve such issue incurred during polymer transfer process of CVD-grown graphene, various approaches including thermal annealing, chemical cleaning, mechanical cleaning have been tried but were not successful in getting rid of polymeric residues. On the other hand, lithographical patterning of graphene is an essential step in any form of microelectronic processing and most of conventional lithographic techniques employ photoresist for the definition of graphene patterns on substrates. But, application of photoresist is undesirable because of the presence of residual polymers that contaminate the graphene surface consistent with the effects generated during transfer process. Therefore, in order to fully utilize the excellent properties of CVD-grown graphene, new approach of transfer and patterning techniques which can avoid polymeric residue problem needs to be developed. In this work, we carried out transfer and patterning process simultaneously with no polymeric residue by using a metal etch mask. The patterned thin gold layer was deposited on CVD-grown graphene instead of photoresists in order to make much cleaner and smoother surface and then transferred onto a desired substrate with PMMA, which does not directly contact with graphene surface. We compare the surface properties and patterning morphology of graphene by scanning electron microscopy (SEM), atomic force microscopy(AFM) and Raman spectroscopy. Comparison with the effect of residual polymer and metal on performance of graphene FET will be discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.408-408
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• 2012

It is well known that magnetic random access memory (MRAM) is nonvolatile memory devices using ferromagnetic materials. MRAM has the merits such as fast access time, unlimited read/write endurance and nonvolatility. Although DRAM has many advantages containing high storage density, fast access time and low power consumption, it becomes volatile when the power is turned off. Owing to the attractive advantages of MRAM, MRAM is being spotlighted as an alternative device in the future. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal- oxide semiconductor (CMOS). MTJ stacks are composed of various magnetic materials. FePt thin films are used as a pinned layer of MTJ stack. Up to date, an inductively coupled plasma reactive ion etching (ICPRIE) method of MTJ stacks showed better results in terms of etch rate and etch profile than any other methods such as ion milling, chemical assisted ion etching (CAIE), reactive ion etching (RIE). In order to improve etch profiles without redepositon, a better etching process of MTJ stack needs to be developed by using different etch gases and etch parameters. In this research, influences of $O_2$ gas on the etching characteristics of FePt thin films were investigated. FePt thin films were etched using ICPRIE in $CH_4/O_2/Ar$ gas mix. The etch rate and the etch selectivity were investigated in various $O_2$ concentrations. The etch profiles were studied in varying etch parameters such as coil rf power, dc-bias voltage, and gas pressure. TiN was employed as a hard mask. For observation etch profiles, field emission scanning electron microscopy (FESEM) was used.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.167-167
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• 2011

Magnetic random access memory (MRAM) is one of the prospective semiconductor memories for next generation. It has the excellent features including nonvolatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack is composed of various magnetic materials, metals, and a tunneling barrier layer. For the successful realization of high density MRAM, the etching process of magnetic materials should be developed. Among various magnetic materials, FePt has been used for pinned layer of MTJ stack. The previous etch study of FePt magnetic thin films was carried out using $CH_4/O_2/NH_3$. It reported only the etch characteristics with respect to the variation of RF bias powers. In this study, the etch characteristics of FePt thin films have been investigated using an inductively coupled plasma reactive ion etcher in various etch chemistries containing $CH_4$/Ar and $CH_4/O_2/Ar$ gas mixes. TiN thin film was employed as a hard mask. FePt thin films are etched by varying the gas concentration. The etch characteristics have been investigated in terms of etch rate, etch selectivity and etch profile. Furthermore, x-ray photoelectron spectroscopy is applied to elucidate the etch mechanism of FePt thin films in $CH_4$/Ar and $CH_4/O_2/Ar$ chemistries.

• 한국기계가공학회지
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• 제18권2호
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• pp.38-43
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• 2019

Electrochemical etching is a popular process to apply metal patterning in various industries. In this study, the electrochemical etching using a patterned copper layer was proposed to fabricate multilayered structures. The process consists of electrodeposition, laser patterning, and electrochemical etching, and a repetition of this process enables the production of multilayered structures. In the fabrication of a multilayered structure, an etch factor that reflects the etched depth and pattern size should be considered. Hence, the etch factor in the electrochemical etching process using the copper layer was calculated. After the repetition process of electrochemical etching using copper layers, the surface characteristics of the workpiece were analyzed by EDS analysis and surface profilometer. As a result, multilayered structures with various shapes were successfully fabricated via electrochemical etching using copper layers.