• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.469-472
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• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.

• 한국세라믹학회지
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• 제43권1호
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• pp.42-47
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• 2006

In this paper, we prepared high-quality ZnO thin films for application of FBAR (Film Bulk Acoustic Resonator) by using pulse DC magnetron sputtering. To prevent the formation of low dielectric layers between metal and piezoelectric layer, Ru film of 30 nm thickness was used as a buffer layer. In addition we investigated the influence of annealing condition with various temperatures. As the annealing temperature increased, the crystalline orientation with the preference of (002) c-axis and resistance properties improved. The single resonator which was fabricated at $500^{\circ}C$ exhibited the resonance frequency and the return loss 0.99 GHz and 15 dB, respectively. This work demonstrates potential feasibility for the use of thin film Ru buffer layers and the optimization of annealing condition.

• Progress in Superconductivity
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• 제11권2호
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• pp.100-105
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• 2010

Reel-to-reel deposition of $Y_2O_3$ has been performed on Ni-5%W metal substrates using the RF-sputtering method. The epitaxial orientation of $Y_2O_3$ buffer layers to the base bi-axially textured substrate was well identified using ${\theta}-2{\theta}$, out-of-plane ($\omega$), and in-plane ($\phi$) scans in X-ray diffraction analysis. The optimization of $Y_2O_3$ seed layers in reel-to-reel fashion were investigated varying the deposition temperature, sputtering power, and pressure for its significant roles for the following buffer stacks and superconducting layers. $Y_2O_3$ were all grown epitaxially on bi-axially textured metal substrates at 380 watts and 5 mTorr in the temperature range of $600-740^{\circ}C$ with higher $Y_2O_3$ (400) intensities at ${\sim}710^{\circ}C$. It was found that the $\Delta\omega$ values were $1-2^{\circ}$ lower but the $\Delta\phi$ values were above $1^{\circ}$ higher than that of Ni-W substrates. As the sputtering power increased from 340 to 380 watts, $\Delta\omega$ and $\Delta\phi$ values showed decreased tendency. Even in the small window of deposition pressure of 3-7 mTorr, the $Y_2O_3$ (400) intensities increased and $\Delta\omega$ and $\Delta\phi$ values were reduced as sputtering pressure increased.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2009년도 Korea Superconductivity Society Meeting 2009
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• pp.99-99
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• 2009

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.133.4-133
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• 1998

• 대한금속재료학회지
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• 제47권10호
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• pp.681-685
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• 2009

$CeO_2$ buffer layers have been deposited on YSZ single crystal substrates via a radio-frequency sputtering method. We focused on the texture development of $CeO_2$ with out-of-plane alignment and its effects on a superconducting YBCO layer, which was deposited by metal organic deposition. $CeO_2$ layers were grown epitaxially on single crystal YSZ substrates and subsequent YBCO layers were also grown epitaxially from $CeO_2$ layers. It was observed that the intensity of $CeO_2$(200) decreased with deposition temperature. ${\theta}-2{\theta}$ scan FWHM values of $CeO_2$(200) were inversely proportional to the peak intensities of $CeO_2$(200). The sample with the lowest $CeO_2$(200) intensity and poor out-of-plane alignment showed a strong reaction with the MOD-YBCO layer resulting in a thicker $BaCeO_3$ layer. The texture and superconducting property of the YBCO layer were affected indirectly by the formation of a $BaCeO_3$ layer at the interface between the $CeO_2$ and YBCO layers.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국재료학회지
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• 제29권2호
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• pp.106-115
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• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• 대한금속재료학회지
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• 제49권10호
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• pp.811-817
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• 2011

In this study, we have investigated the role of a metal oxide hole injection layer (HIL) between an Indium Tin Oxide (ITO) electrode and an organic hole transporting layer (HTL) in organic light emitting diodes (OLEDs). Nickel Oxide films were deposited at different deposition times of 0 to 60 seconds, thus leading to a thickness from 0 to 15 nm on ITO/glass substrates. To study the influence of NiO film thickness on the properties of OLEDs, the relationships between NiO/ITO morphology and surface properties have been studied by UV-visible spectroscopy measurements and AFM microscopy. The dependences of the I-V-L properties on the thickness of the NiO layers were examined. Comparing these with devices without an NiO buffer layer, turn-on voltage and luminance have been obviously improved by using the NiO buffer layer with a thickness smaller than 10 nm in OLEDs. Moreover, the efficiency of the device ITO/NiO (< 5 nm)/NPB/$Alq_3$/ LiF/Al has increased two times at the same operation voltage (8V). Insertion of a thin NiO layer between the ITO and HTL enhances the hole injection, which can increase the device efficiency and decrease the turn-on voltage, while also decreasing the interface roughness.

• 한국재료학회지
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• 제30권10호
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• pp.566-572
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• 2020

In the recent years, thin film solar cells (TFSCs) have emerged as a viable replacement for crystalline silicon solar cells and offer a variety of choices, particularly in terms of synthesis processes and substrates (rigid or flexible, metal or insulator). Among the thin-film absorber materials, SnS has great potential for the manufacturing of low-cost TFSCs due to its suitable optical and electrical properties, non-toxic nature, and earth abundancy. However, the efficiency of SnS-based solar cells is found to be in the range of 1 ~ 4 % and remains far below those of CdTe-, CIGS-, and CZTSSe-based TFSCs. Aside from the improvement in the physical properties of absorber layer, enormous efforts have been focused on the development of suitable buffer layer for SnS-based solar cells. Herein, we investigate the device performance of SnS-based TFSCs by introducing double buffer layers, in which CdS is applied as first buffer layer and ZnMgO films is employed as second buffer layer. The effect of the composition ratio (Mg/(Mg+Zn)) of RF sputtered ZnMgO films on the device performance is studied. The structural and optical properties of ZnMgO films with various Mg/(Mg+Zn) ratios are also analyzed systemically. The fabricated SnS-based TFSCs with device structure of SLG/Mo/SnS/CdS/ZnMgO/AZO/Al exhibit a highest cell efficiency of 1.84 % along with open-circuit voltage of 0.302 V, short-circuit current density of 13.55 mA cm^-2, and fill factor of 0.45 with an optimum Mg/(Mg + Zn) ratio of 0.02.