• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.7-14
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• 2017

Due to the recent advances in Phage-Change Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.3 no.1
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• pp.66-71
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• 2003

In the past, when there were few vehicles on the road, the T.O.D.(Time of Day) traffic signal worked very well. The T.O.D. signal operates on a preset signal cycling which cycles on the basis of the average number of average passenger cars in the memory device of an electric signal unit. Today, with increasing traffic and congested roads, the conventional traffic light creates startup-delay time and end lag time so that thirty to forty-five percent efficiency in traffic handling is lost, as well as adding to fuel costs. To solve this problem, this paper proposes a new concept of optimal green time algorithm, which reduces average vehicle waiting time while improving average vehicle speed using fuzzy rules and neural networks. Through computer simulation, this method has been proven to be much more efficient than fixed time interval signals. Fuzzy Neural Network will consistanly improve average waiting time, vehicle speed, and fuel consumption.

• ETRI Journal
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• v.46 no.3
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• pp.379-391
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• 2024

To meet increasing traffic requirements in mobile networks, small base stations (SBSs) are densely deployed, overlapping existing network architecture and increasing system capacity. However, densely deployed SBSs increase energy consumption and interference. Although these problems already exist because of densely deployed SBSs, even more SBSs are needed to meet increasing traffic demands. Hence, base station (BS) switching operations have been used to minimize energy consumption while guaranteeing quality-of-service (QoS) for users. In this study, to optimize energy efficiency, we propose the use of deep reinforcement learning (DRL) to create a BS switching operation strategy with a traffic prediction model. First, a federated long short-term memory (LSTM) model is introduced to predict user traffic demands from user trajectory information. Next, the DRL-based BS switching operation scheme determines the switching operations for the SBSs using the predicted traffic demand. Experimental results confirm that the proposed scheme outperforms existing approaches in terms of energy efficiency, signal-to-interference noise ratio, handover metrics, and prediction performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.71-76
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• 2022

Buffer cache bridges the performance gap between memory and storage, but its effectiveness is limited due to periodic flush, performed to prevent data loss in smartphones. This paper shows that selective flushing technique with small persistent memory can reduce the flushing overhead of smartphone buffer cache significantly. This is due to our I/O analysis of smartphone applications in that a certain hot data account for most of file writes, while a large proportion of file data incurs single-writes. The proposed selective flushing policy performs flushing to persistent memory for frequently updated data, and storage flushing is performed only for single-write data. This eliminates storage write traffic and also improves the space efficiency of persistent memory. Simulations with popular smartphone application I/O traces show that the proposed policy reduces write traffic to storage by 24.8% on average and up to 37.8%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.22 no.5
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• pp.1-18
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• 2023

With the recent developments in big data and deep learning, a variety of traffic information is collected widely and used for traffic operations. In particular, long short-term memory (LSTM) is used in the field of traffic information prediction with time series characteristics. Since trends, seasons, and cycles differ due to the nature of time series data input for an LSTM, a trial-and-error method based on characteristics of the data is essential for prediction models based on time series data in order to find hyperparameters. If a methodology is established to find suitable hyperparameters, it is possible to reduce the time spent in constructing high-accuracy models. Therefore, in this study, a traffic information prediction model is developed based on highway vehicle detection system (VDS) data and LSTM, and an impact assessment is conducted through changes in the LSTM evaluation indicators for each hyperparameter. In addition, a methodology for finding hyperparameters suitable for predicting highway traffic information in the transportation field is presented.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.301-308
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• 2003

In this paper, we propose a multicast ATM switch that reduces traffic load by using the method of storing unicast cells and multicast cells separately according to the type of the cells. The switch is based on a shared memory type to reduce HOL blocking and deadlock. In the proposed switch, we use a control scheme that schedules stored cells to output ports to reduce the loss of traffic cells and to output effectively. We analyzed the Performance of the proposed switch through the computer simulation and the results have shown the effectiveness of the switch.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.1098-1105
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• 1999

The caches in distributed shared memory systems enhance the performance by reducing memory access latency and communication overhead, but they must solve the cache coherence problem. This paper proposes a new directory protocol to solve the cache coherence problem and to improve the system performance in distributed shared memory systems. To maintain the cache coherence of shared data, processors within a limited distance reduce the communication overhead by using a bit-vector like the full directory scheme. Processors over a limited distance store pointers in a directory pool. Since the bit-vector and the directory pool remove the unnecessary cache invalidations, the proposed scheme reduces the communication traffic and improves the system performance. The dynamic limited directory scheme reduces the communication traffic up to 66 percents compared with the limited directory scheme and the number of directory access up to 27 percents compared with the dynamic pointer allocation scheme.

• Journal of Communications and Networks
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• v.9 no.3
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• pp.330-341
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• 2007

This work analyzes the performance of the parallel packet switch (PPS) with a sliding window (SW) method. The PPS involves numerous packet switches that operate independently and in parallel. The conventional PPS dispatch algorithm adopts a round robin (RR) method. The class of PPS is characterized by deployment of parallel low-speed switches whose all memory buffers run more slowly than the external line rate. In this work, a novel SW packet switching method for PPS, called SW-PPS, is proposed. The SW-PPS employs memory space more effectively than the existing PPS using RR algorithm. Under identical Bernoulli and bursty data traffic, the SW-PPS provided significantly improved performance when compared to PPS with RR method. Moreover, this investigation presents a novel mathematical analytical model to evaluate the performance of the PPS using RR and SW method. Under various operating conditions, our proposed model and analysis successfully exhibit these performance characteristics including throughput, cell delay, and cell drop rate.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1922-1940
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• 2019

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.