• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• (The) Korean Journal of Educational Psychology
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• v.31 no.4
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• pp.819-845
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• 2017

Although testing is usually done for purposes of assessment, previous research over the past 100 years indicates that testing is an effective tool for learning. Testing or retrieval practice of previously studied materials can enhance learning of that previously studied information and/or learning of subsequently presented new information. The former is referred to as the backward effect of testing whereas the latter is referred to as the forward effect of testing. Thus far, however, the literature has not isolated these two effects and most previous research focused on the backward effect. Only recent laboratory research provided evidence that there is a forward effect of testing. The present study provides a review of research on this forward and backward effect of testing, focusing on testing procedures of the effects, empirical evidence, current theoretical explanations, and issues to resolve in order to make use of testing effect in educational settings. The reviews clearly show that testing enhances memory of previously learned information by working as memory modifier and learning of newly presented information by affecting learners' metacognition, implying that testing is not just an assessment of learning, but also an effective tool for learning.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.26-33
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• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• Korean Journal of Adult Nursing
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• v.18 no.3
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• pp.468-478
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• 2006

Purpose: The purpose of this study were to find out the degree of memory decline and to confirm its correlated factors in old adults. Method: The subjects consisted of 68 old adults over the age 65 who living in Busan. Data were collected by the interview method, using a structured questionnaire and the testing method on the memory performance. Results: The old adults' memory performances declined in tasks of immediately word recall, delayed word recall, and face recognition and increased slightly in word recognition over 2 years. However, there was only significant difference in delayed word recall task. The significant variables to predict memory decline were age, literacy, depression, locus, and strategy. Conclusion: The memory decline of old adults wasn't more serious problem than the perceived one. There needs to be some intervention programs to prevent memory decline for the elderly.

• Smart Structures and Systems
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• v.14 no.5
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• pp.883-900
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• 2014

Shape memory alloys (SMA) can dissipate energy through hysteresis cycles without significant residual deformation. This paper describes the fabrication and testing of copper-based SMA hourglass-shaped plates for use in energy dissipation devices and the development of a numerical model to reproduce the experiments. The plates were tested under cyclic flexural deformations, showing stable hysteresis cycles without strength degradation. A detailed nonlinear numerical model was developed and validated with the experimental data, using as input the constitutive relationship for the material determined from cyclic tests of material coupons under tension loading. The model adequately reproduces the experimental results. The study is focused on the exploitation of SMA in the martensite phase.

• KEPCO Journal on Electric Power and Energy
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• v.8 no.2
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• pp.93-96
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• 2022

The boiler tubes of thermal power plants are exposed to harsh environment of high temperature and high pressure, and the deterioration state of materials rapidly increases. In particular, parent material and welds of the materials used are subjected to a temperature change and various constraints, resulting in deformation and its growth, resulting in frequent leakage accidents caused by tube failure. The power plant checks the integrity of boiler tubes through non-destructive testing as it may act as huge costs loss and limitation of power supply during power station shutdown period due to boiler tube leakage. However, the current non-destructive testing is extremely limited in the field to detect micro cracks. In this study, the ability of metal magnetic memory technique to detect flaws of size that are difficult to inspect by the visual or general non-destructive methods was verified in the early stage of their occurrence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1038-1045
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• 1994

In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.