• Title/Summary/Keyword: Memory school

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Smart Air Condition Load Forecasting based on Thermal Dynamic Model and Finite Memory Estimation for Peak-energy Distribution

  • Choi, Hyun Duck;Lee, Soon Woo;Pae, Dong Sung;You, Sung Hyun;Lim, Myo Taeg
    • Journal of Electrical Engineering and Technology
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    • v.13 no.2
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    • pp.559-567
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    • 2018
  • In this paper, we propose a new load forecasting method for smart air conditioning (A/C) based on the modified thermodynamics of indoor temperature and the unbiased finite memory estimator (UFME). Based on modified first-order thermodynamics, the dynamic behavior of indoor temperature can be described by the time-domain state-space model, and an accurate estimate of indoor temperature can be achieved by the proposed UFME. In addition, a reliable A/C load forecast can be obtained using the proposed method. Our study involves the experimental validation of the proposed A/C load forecasting method and communication construction between DR server and HEMS in a test bed. Through experimental data sets, the effectiveness of the proposed estimation method is validated.

Comparison of Efficiency of Flash Memory Device Structure in Electro-Thermal Erasing Configuration (플래시메모리소자의 구조에 대한 열적 데이터 삭제 효율성 비교)

  • Kim, You-Jeong;Lee, Seung-Eun;Lee, Khwang-Sun;Park, Jun-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.35 no.5
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    • pp.452-458
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    • 2022
  • The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

Research on Mac OS X Physical Memory Analysis (Mac OS X 물리 메모리 분석에 관한 연구)

  • Lee, Kyeong-Sik;Lee, Sang-Jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.21 no.4
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    • pp.89-100
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    • 2011
  • Physical memory analysis has been an issue on a field of live forensic analysis in digital forensics until now. It is very useful to make the result of analysis more reliable, because record of user behavior and data can be founded on physical memory although process is hided. But most memory analysis focuses on windows based system. Because the diversity of target system to be analyzed rises up, it is very important to analyze physical memory based on other OS, not Windows. Mac OS X, has second market share in Operating System, is operated by loading kernel image to physical memory area. In this paper, We propose a methodology for physical memory analysis on Mac OS X using symbol information in kernel image, and acquire a process information, mounted device information, kernel information, kernel extensions(eg. KEXT) and system call entry for detecting system call hooking. In additional to the methodology, we prove that physical memory analysis is very useful though experimental study.

Long Memory Characteristics in the Korean Stock Market Volatility

  • Cho, Sinsup;Choe, Hyuk;Park, Joon Y
    • Communications for Statistical Applications and Methods
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    • v.9 no.3
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    • pp.577-594
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    • 2002
  • For the estimation and test of long memory feature in volatilities of stock indices and individual companies semiparametric approach, Geweke and Porter-Hudak (1983), is employed. Empirical study supports the strong evidence of volatility persistence in Korean stock market. Most of indices and individual companies have the feature of long term dependence of volatility. Hence the short memory models are unable to explain the volatilities in Korean stock market.

Inhibitory Effects of Eucommia ulmoides Oliv. Bark on Scopolamine-Induced Learning and Memory Deficits in Mice

  • Kwon, Seung-Hwan;Ma, Shi-Xun;Joo, Hyun-Joong;Lee, Seok-Yong;Jang, Choon-Gon
    • Biomolecules & Therapeutics
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    • v.21 no.6
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    • pp.462-469
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    • 2013
  • Eucommia ulmoides Oliv. Bark (EUE) is commonly used for the treatment of hypertension, rheumatoid arthritis, lumbago, and ischialgia as well as to promote longevity. In this study, we tested the effects of EUE aqueous extract in graded doses to protect and enhance cognition in scopolamine-induced learning and memory impairments in mice. EUE significantly improved the impairment of short-term or working memory induced by scopolamine in the Y-maze and significantly reversed learning and memory deficits in mice as measured by the passive avoidance and Morris water maze tests. One day after the last trial session of the Morris water maze test (probe trial session), EUE dramatically increased the latency time in the target quadrant in a dose-dependent manner. Furthermore, EUE significantly inhibited acetylcholinesterase (AChE) and thiobarbituric acid reactive substance (TBARS) activities in the hippocampus and frontal cortex in a dose-dependent manner. EUE also markedly increased brain-derived neurotrophic factor (BDNF) and phosphorylation of cAMP element binding protein (CREB) in the hippocampus of scopolamine-induced mice. Based on these findings, we suggest that EUE may be useful for the treatment of cognitive deficits, and that the beneficial effects of EUE are mediated, in part, by cholinergic signaling enhancement and/or protection.

Research Trend of High Aspect Ratio Contact Etching used in Semiconductor Memory Device Manufacturing (반도체 메모리 소자 제조에서 High Aspect Ratio Contact 식각 연구 동향)

  • Hyun-Woo Tak;Myeong-Ho Park;Jun-Soo Lee;Chan-Hyuk Choi;Bong-Sun Kim;Jun-Ki Jang;Eun-Koo Kim;Dong-Woo Kim;Geun-Young Yeom
    • Journal of the Korean institute of surface engineering
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    • v.57 no.3
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    • pp.165-178
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    • 2024
  • In semiconductor memory device manufacturing, the capability for high aspect ratio contact (HARC) etching determines the density of memory device. Given that there is no standardized definition of "high" in high aspect ratio, it is crucial to continuously monitor recent technology trends to address technological gaps. Not only semiconductor memory manufacturing companies such as Samsung Electronics, SK Hynix, and Micron but also semiconductor manufacturing equipment companies such as Lam Research, Applied Materials, Tokyo Electron, and SEMES release annual reports on HARC etching technology. Although there is a gap in technological focus between semiconductor mass production environments and various research institutes, the results from these institutes significantly contribute by demonstrating fundamental mechanisms with empirical evidence, often in collaboration with industry researchers. This paper reviews recent studies on HARC etching and the study of dielectric etching in various technologies.

Analysis Algorithm for Memory BISR as Imagination Zone (가상 구역에 따른 메모리 자가 치유에 대한 분석 알고리즘)

  • Park, Jae-Heung;Shim, Eun-Sung;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.73-79
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    • 2009
  • With the advance of VLSI technology, the capacity and density of memories are rapidly growing. In this paper we proposed MRI (Memory built-in self Repair Imagination zone) as reallocation algorithm. All faulty cells of embedded memory are reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

Receding Horizon Finite Memory Controls for Output Feedback Controls of Discrete-Time State Space Models

  • Han, Soo-Hee;Kwon, Wook-Hyun
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1896-1900
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    • 2003
  • In this paper, a new type of output feedback control, called a receding horizon finite memory control (RHFMC), is proposed for stochastic discrete-time state space systems. Constraints such as linearity and finite memory structure with respect to an input and an output, and unbiasedness from the optimal state feedback control are required in advance. The proposed RHFMC is chosen to minimize an optimal criterion with these constraints. The RHFMC is obtained in an explicit closed form using the output and input information on the recent time interval. It is shown that the RHFMC consists of a receding horizon control and an FIR filter. The stability of the RHFMC is investigated for stochastic systems.

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Memory-Efficient NBNN Image Classification

  • Lee, YoonSeok;Yoon, Sung-Eui
    • Journal of Computing Science and Engineering
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    • v.11 no.1
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    • pp.1-8
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    • 2017
  • Naive Bayes nearest neighbor (NBNN) is a simple image classifier based on identifying nearest neighbors. NBNN uses original image descriptors (e.g., SIFTs) without vector quantization for preserving the discriminative power of descriptors and has a powerful generalization characteristic. However, it has a distinct disadvantage. Its memory requirement can be prohibitively high while processing a large amount of data. To deal with this problem, we apply a spherical hashing binary code embedding technique, to compactly encode data without significantly losing classification accuracy. We also propose using an inverted index to identify nearest neighbors among binarized image descriptors. To demonstrate the benefits of our method, we apply our method to two existing NBNN techniques with an image dataset. By using 64 bit length, we are able to reduce memory 16 times with higher runtime performance and no significant loss of classification accuracy. This result is achieved by our compact encoding scheme for image descriptors without losing much information from original image descriptors.

Latency Hiding based Warp Scheduling Policy for High Performance GPUs

  • Kim, Gwang Bok;Kim, Jong Myon;Kim, Cheol Hong
    • Journal of the Korea Society of Computer and Information
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    • v.24 no.4
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    • pp.1-9
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    • 2019
  • LRR(Loose Round Robin) warp scheduling policy for GPU architecture results in high warp-level parallelism and balanced loads across multiple warps. However, traditional LRR policy makes multiple warps execute long latency operations at the same time. In cases that no more warps to be issued under long latency, the throughput of GPUs may be degraded significantly. In this paper, we propose a new warp scheduling policy which utilizes latency hiding, leading to more utilized memory resources in high performance GPUs. The proposed warp scheduler prioritizes memory instruction based on GTO(Greedy Then Oldest) policy in order to provide reduced memory stalls. When no warps can execute memory instruction any more, the warp scheduler selects a warp for computation instruction by round robin manner. Furthermore, our proposed technique achieves high performance by using additional information about recently committed warps. According to our experimental results, our proposed technique improves GPU performance by 12.7% and 5.6% over LRR and GTO on average, respectively.