• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.2
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• pp.467-479
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• 2022

Working memory (WM), which plays a vital role in daily activities, is a memory system that temporarily stores and processes information when people are engaged in complex cognitive activities. The influence of music on WM has been widely studied. In this work, we conducted a series of n-back memory experiments with different task difficulties and multiple trials on 14 subjects under the condition of no music and Alpha wave leading music. The analysis of behavioral data show that the change of music condition has significant effect on the accuracy and time of memory reaction (p<0.01), both of which are improved after the stimulation of Alpha wave music. Behavioral results also suggest that short-term training has no significant impact on working memory. In the further analysis of electrophysiology (EEG) data recorded in the experiment, auto-regressive (AR) model is employed to extract features, after which an average classification accuracy of 82.9% is achieved with support vector machine (SVM) classifier in distinguishing between before and after WM enhancement. The above findings indicate that Alpha wave leading music can improve WM, and the combination of AR model and SVM classifier is effective in detecting the brain activity changes resulting from music stimulation.

• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.1-11
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• 2012

As process technology scales down, the number of cores integrated into a processor increases dramatically, leading to significant performance improvement. Especially, the GPU(Graphics Processing Unit) containing many cores can provide high computational performance by maximizing the parallelism. In the GPU architecture, the access latency to the main memory becomes one of the major reasons restricting the performance improvement. In this work, we analyze the performance improvement of the 3D GPU architecture compared to the 2D GPU architecture quantitatively and investigate the potential problems of the 3D GPU architecture. In general, memory instructions account for 30% of total instructions, and global/local memory instructions constitutes 60% of total memory instructions. Therefore, the performance of the 3D GPU is expected to be improved significantly compared to the 2D GPU by reducing the delay of memory instructions. However, according to our experimental results, the 3D architecture improves the GPU performance only by 2% compared to the 2D architecture due to the memory bottleneck, since the performance reduction due to memory bottleneck in the 3D GPU architecture increases by 245% compared to the 2D architecture. This paper provides the guideline for suitable memory design by analyzing the efficiency of the memory architecture in 3D GPU architecture.

• Korean Journal of Mathematics
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• v.24 no.3
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• pp.447-467
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• 2016

We prove the existence of random attractors for the continuous random dynamical systems generated by stochastic damped plate equations with linear memory and additive white noise when the nonlinearity has a critically growing exponent.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1115-1116
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• 2008

Through comparison and evaluation of various HDD systems for PC such as magnetic HDD, Intel turbo memory and Solid State Drive (SSD), an optimized HDD system to improve booting speed proposed. For the study, conventional magnetic HDD, magnetic HDD with Intel turbo memory, SSD and SSD with Intel turbo memory are used. The evaluation is performed based on a full notebook machine with Intel SantaRosa platform and MicroSoft Windows Vista.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.743-744
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• 2006

This paper presents implementation of parallel processing system for image processing. The parallel processing system proposed consisted of 16 processing elements, and multi-access memory system, and interface modules. The multi-access memory system we introduced is made up of a memory module selection, a data routing module, and an address calculation and routing module.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• Journal of Information Technology Applications and Management
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• v.31 no.1
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• pp.177-188
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• 2024

In this research, a cohort of two children, aged 7-8 years, was selected to participate in a specialized three-week training program aimed at enhancing their working memory. The program consisted of three sessions, each lasting approximately 30 minutes. The primary goal was to investigate the impact and developmental trajectory of working memory in school-aged children. Working memory plays a significant role in young children's learning and daily activities. To address the needs of this demographic, products should offer both educational and enjoyable activities that engage working memory. Digital educational tools, known for their flexibility, are suitable for both older individuals and young children. By updating software or modifying content, these tools can be effectively repurposed for young learners without extensive hardware changes, making them both cost-effective and practical. For example, memory training games initially designed for older adults can be adapted for young children by altering images, music, or storylines. Furthermore, incorporating elements familiar to children, like animals, toys, or fairy tales, can increase their engagement in these activities. Historically, working memory capabilities have been assessed predominantly through traditional intelligence tests. However, recent research questions the adequacy of these behavioral measures in accurately detecting changes in working memory. To bridge this gap, the current study utilized electroencephalography (EEG) as a more sophisticated and precise tool for monitoring potential changes in working memory after the training. The research findings were revealing. Participants showed marked improvement in their performance on n-back tasks, a standard measure for evaluating working memory. This improvement post-training strongly supports the effectiveness of the training program. The results indicate that such targeted and structured training programs can significantly enhance the working memory abilities of children in this age group, providing promising implications for educational strategies and cognitive development interventions.

• Transactions on Electrical and Electronic Materials
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• v.15 no.1
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• pp.16-19
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• 2014

Charge trapping nonvolatile memory capacitors with $ZrO_2$ as charge trapping layer were fabricated, and the effects of post annealing atmosphere ($NH_3$ and $N_2$) on their memory storage characteristics were investigated. It was found that the memory windows were improved, after annealing treatment. The memory capacitor after $NH_3$ annealing treatment exhibited the best electrical characteristics, with a 6.8 V memory window, a lower charge loss ~22.3% up to ten years, even at $150^{\circ}C$, and excellent endurance (1.5% memory window degradation). The results are attributed to deep level bulk charge traps, induced by using $NH_3$ annealing.

• Journal of Aerospace System Engineering
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• v.9 no.2
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• pp.7-12
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• 2015

In this paper, we report a non-explosive separation device for a small satellite which utilize a shape memory alloy actuator and spring clamp. In order to increase the preload, the proposed device employs spring clamp that can generate high toque when the shape memory alloy actuator makes the cylinder key unlatch a holding ball effectively. Owing to simple design of separation device configuration, we could obtain good repeatability(up to 30 times activation). Conclusively, we could develop a non-explosive separation device which can reliably activate within 1.2 sec under high preload(up to 300kgf).

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.189-200
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• 2001

This paper proposes a memory allocation model for Real-Time Linux. The proposed model allows users to create several continuous memory regions in an application, to specify an appropriate region allocation policy for each memory region, and to request memory blocks from a necessary memory region. Instead of using single memory management module in order to support the proposed model, we adopt two-layered structure that is consisted of region allocators implementing allocation policies and a region manager controlling regions and region allocator modules. This structure separates allocation policy from allocation mechanism, thus allows system developers to implement same allocation policy using different algorithms in case of need. IN addition, it enables them to implement new allocation policy using different algorithms in case of need. In addition, it enables them to implement new allocation policy easily as long as they preserver predefined internal interfaces, to add the implemented policy into the system, and to remove unnecessary allocation policies from the system, Because the proposed model provides various allocation policies implemented previously, system builders can also reconfigure the system by just selecting most appropriate policies for a specific application without implementing these policies from scratch.