• 대한음성학회지:말소리
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• 제52호
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.384-384
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• 2012

We report nonvolatile memory properties of poly (3, 4-ethylenedioxythiophene) (PEDOT) thin films grown by vapor phase polymerization using FeCl3 as an oxidant. Liquid-bridge-mediated transfer method was employed to remove FeCl3 for generation of pure PEDOT thin films. From the electrical measurement of memory device, we observed voltage induced bipolar resistive switching behavior with ON/OFF ratio of 103 and reproducibility of more than 103 dc sweeping cycles. ON and OFF states were stable up to 104 seconds without significant degradation. Cyclic voltammetry data illustrates resistive switching effect can be attributed to formation and rupture of conducting paths due to oxidation and reduction of PEDOT. The maximum current before reset process was found to be increase linearly with increase in compliance current applied during set process.

• 대한전자공학회논문지
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• 제21권3호
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• pp.19-25
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• 1984

Microprogrammed 디지탈 시스템에서 재프로그램을 위한 가변성을 고려한 제어기억장치의 비트 폭을 최소화시키는 새로운 알고리즘을 제시한다. 본 알고리즘은 비트 폭을 최소화시킴과 동시에 weight가 높은 MOP에 고유영역을 부여함으로써 비트 최소화 과정시에 수반되는 가변성의 손실을 보상할 수 있다. 또 본 알고리즘을 프로그램하여 종래의 연구결과와 비교 검토하여 비트 감소와 가변성이 개선된 것을 중명하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1053-1056
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• 2004

Chunghwa Picture Tubes, LTD. (CPT) has developed a Novel TFT-LCD Driving Techniquel. This new technique is developed in combination with other state-of-the-art image processing solutions such as image compression / decompression, motion detection, and noise reduction. By applying the Novel Driving Technique to the high resolution TFT-LCD, it was found that the response time can be effectively reduced with a lower overall system cost by smaller frame memory requirement, lower EMI by less memory band-width. Likewise, higher display quality can also be achieved in that the unexpected noises generated by over-drive can be eliminated. The Novel TFT-LCD Driving Technique has been successfully implemented to the 30 inch WXGA (1280${\times}$768) resolution TFT LCD commercial TV module. It was found that the quality of moving picture was better improved compared with that of the conventional fast response driving method.

• 대한한의학회지
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• 제27권4호
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• pp.125-134
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• 2006

During the prenatal period, the development of the individual is influenced by a host of environmental factors. Exposure to noise stress during pregnancy was determined to result in the retardation of growth, a reduction in neurogenesis, and an impairment of spatial learning ability in the rat pups. In the present study, we have attempted to characterize the effects of prenatal treatment with Cnidium officinale Makino on spatial memory and neurogenesis in the hippocampus of rat pups born from maternal rats exposed to noise stress during pregnancy. Prenatal treatment with Cnidium officinale Makino was shown to increase neurogenesis and enhanced spatial learning ability in rat pups born from maternal rats exposed to noise stress. In this study, we have determined that prenatal treatment with Cnidium officinale Makino can stimulate spatial development and neurogenesis in the brain of the fetuses exposed to prenatal stresses.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2001년도 춘계 학술대회논문집
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• pp.38-44
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• 2001

An efficient Gauss-Seidel time integration scheme is developed for solving the Euler and Navier-Stokes equations on unstructured meshes. Roe's FDS is used for the explicit residual computations and van Leer's FVS for evaluating implicit flux Jacobian. To reduce the memory requirement to a minimum level, off-diagonal flux Jacobian contributions are repeatedly calculated during the Gauss-Seidel sub-iteration process. Computational results based on the present scheme show that approximately $15\%$ of CPU time reduction is achieved while maintaining the memory requirement level to $50-60\%$ of the original Gauss-Seidel scheme.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.82-85
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• 1998

Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

• Journal of information and communication convergence engineering
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• 제15권2호
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• pp.117-122
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• 2017

Three-dimensional integrated circuits (3D ICs), starting with memory cubes, have entered the mainstream recently. The benefits many predicted in the past are indeed delivered, including higher memory bandwidth, smaller form factor, and lower energy. However, 3D ICs have yet to find their deployment in aerospace applications. In this paper we first present key design tools and methodologies for high performance, low power, and reliable 3D ICs that mainly target terrestrial applications. Next, we discuss research needs to extend their capabilities to ensure reliable operations under the harsh space environments. We first present a design methodology that performs fine-grained partitioning of functional modules in 3D ICs for power reduction. Next, we discuss our multi-physics reliability analysis tool that identifies thermal and mechanical reliability trouble spots in the given 3D IC layouts. Our tools will help aerospace electronics designers to improve the reliability of these 3D IC components while not degrading their energy benefits.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.80-90
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• 2016

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology