• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.48-54
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• 2008

This paper analyzes cost tradeoffs between memory usage and computation for window-based operators in data stream environments. It identifies generic operator network constructs, and sets up a cost model for the estimation of the expected memory reduction and the computation overheads when window memory relocations are applied to each operator network construct. This cost model helps to identify the utility of window memory relocations. It also helps to apply window memory relocation to improve a query execution plan to save memory usage. The proposed approach contributes to expand the scope of query processing and optimization in data stream environments. It also provides a basis to develop a cost estimation model for the query optimization using window memory relocations.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2690-2700
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• 1997

This paper presents parallel sorting algorithm, SHARED-MEMORY-BS and REDUCED-BS, which are implemented on shared-memory parallel computers. These algorithm sort N keys in $O(log^2N)$ time. REDUCED-BS users a parity strategy which gives an idea for the efficient usage of the local memory associated with each processor. By taking advantage of the local memory associated with each processor, the communication of REDUCED-BS is decreased by approximately half that of SHARED-MEMORY-BS. On the basis of alleviating the communication, the algorithm REDUCED-BS results in a significant improvement of performance.

• Journal of the Korean Operations Research and Management Science Society
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• v.39 no.4
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• pp.19-31
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• 2014

We study parallel processing techniques for the R programming language of high performance computing technology. In this study, we used massively parallel computing system which has 25,408 cpu cores. We conducted a performance evaluation of a distributed memory system using MPI and of a the shared memory system using OpenMP. Our findings are summarized as follows. First, For some particular algorithms, parallel processing is about 150 times faster than serial processing in R. Second, the distributed memory system gets faster as the number of nodes increases while shared memory system is limited in the improvement of performance, due to the limit of the number of cpus in a single system.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.4
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• pp.217-228
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• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

• Korean Journal of Biological Psychiatry
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• v.4 no.2
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• pp.237-245
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• 1997

The study was designed to evaluate the significant roles of SSRI in rat of depression model. Chronic exposure to mild unpredictable stress has been found to depress the consumption of sweet 1% sucrose solutions in the Sprague-Dawley rats. We applied the variety of 11 types of stress regimens and identified depressive behaviours(developed by Willner) in 70 Sprague-Dawley rats. Rats in experiments were stratified into 6 groups, ie ; 3 kinds of SSRI(paroxetine, fluoxetine, sertraline), clomipramine, choline and saline control. Memory function was evaluated by passive avoidance learning and retention test. The authors determined how long memory retention would remain improved with 24 hour, 1 week, 2 weeks, 3 weeks, and 4 weeks at training-testing interval in depressive states of the Sprague-Dawley rats. The results were as follows ; 1) There were no significant differences between the 6 groups at the 24 hour training-testing interval. 2) The paroxetine treated group showed significant differences from the control group at the 1 week and 2 weeks training-testing interval. 3) The paroxetine and the fluoxetine treated groups showed singificant differences from the control group at 3 week training-testing interval. 4) The paroxetine and the choline treated groups showed significant differences from the control group at 4 week training-testing interval. In summary, paroxetine had an effect on long term memory processing from 1st week to 4th week. Also, fluoxetine(at 3rd week) and choline(at 4th week) had effect on long term memory processing. Sertraline, clomipramine were ineffective on memory processing during 4 weeks observation. Possible explanations why paroxetine had early effect on memory processing than the other selective serotonin reuptake inhibitors are rapid bioavailability, which is the characteristics of pharmacokinetics of paroxetine. In clinical situation, author carefully suggest that SSRI would be beneficial to improve the memory function caused by depressive neurochemical changes.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.865-868
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• 2001

TCM offers considerable coding gains without compromising bandwidth or signal power. But TCM decoder is more complex than convolutional Viterbi decoder. Because, the number of branches exponentially increased by the constraint length and input symbol bits. The parallelism of ACS and memory management technique of SPMM is one of the important factor for speed-up and hardware complexity. This paper proposes a multi-processing technique of ACS and also gives a memory management technique of SPMM in TCM decoders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• International Journal of Knowledge Content Development & Technology
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• v.5 no.2
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• pp.75-101
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• 2015

In this paper, we investigate the notion of error correction memory applied to technical texts. The main purpose is to introduce flexibility and context sensitivity in the detection and the correction of errors related to Constrained Natural Language (CNL) principles. This is realized by enhancing error detection paired with relatively generic correction patterns and contextual correction recommendations. Patterns are induced from previous corrections made by technical writers for a given type of text. The impact of such an error correction memory is also investigated from the point of view of the technical writer's cognitive activity. The notion of error correction memory is developed within the framework of the LELIE project an experiment is carried out on the case of fuzzy lexical items and negation, which are both major problems in technical writing. Language processing and knowledge representation aspects are developed together with evaluation directions.