• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.27-32
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• 2021

This paper proposes an energy-efficient cache and memory management scheme for next-generation IoT devices. The proposed scheme adopts a low-power phase-change memory (PCM) as the main memory of IoT devices, aims at minimizing the write traffic to PCM, which is vulnerable to write operations. Specifically, when a cache block of the last-level cache memory is flushed to main memory, the cache block that causes less writes to PCM is preferentially replaced by tracking the modifications of each cache line that constitutes the cache block. In addition, by considering the reference bit of the cache block and the dirty bit of the cache lines, our scheme reduces the energy consumption without degrading the memory system performances. Through simulations using SPEC benchmarks, it is shown that the proposed scheme reduces the write traffic to PCM by 34.6% on average and the power consumption by 28.9%, without memory performance degradations.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.6
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• pp.599-603
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• 2008

Flash memory has its unique characteristics: the write operation is much more costly than the read operation and in-place updating is not allowed. In this paper, we analyze how these characteristics of flash memory affect the performance of clustering and non-clustering in record management, and shows that non-clustering is more suitable in flash memory environment, which does not hold in disk environment. Also, we discuss the problems of the existing non-clustering method, and identify considerable designing factors of record management method in flash memory environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.514-523
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• 2017

In this paper, we propose Adaptive Writeback-aware Cache management (AWC) to prolong the lifetime of non-volatile main memory systems by reducing the number of writebacks. The last-level cache in AWC is partitioned into Least Recently Used (LRU) segment and LRU using Dirty block Precedence (DP-LRU) segment. The DP-LRU segment evicts clean blocks first for giving reuse opportunity to dirty blocks. AWC can also determine the efficient size of DP-LRU segment for reducing the number of writebacks according to memory access patterns of programs. In the performance evaluation, we showed that AWC reduced the number of writebacks up to 29% and 46%, and saved the energy of a main memory system up to 23% and 49% in a single-core and multi-core, respectively. AWC also reduced the runtime by 1.5% and 3.2% on average compared to previous cache managements for non-volatile main memory systems, in a single-core and a multi-core, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.143-148
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• 2017

Flash Memory which is light and strong external shock as storage of small electronics like smartphone, digital camera, car black box has been widely used. Since the operation speed of the read operation and the write operation are different from each other, and the flash memory has the feature that it is not possible to overwrite, the delete operation is added to solve these problems. Wear-leveling must also be considered, since the number of erase times of the flash memory is limited. Many studies have been conducted on the substitutional algorithms of flash memory based on these characteristics of recent flash memories. So, to solve the problem that has existing buffer replacement algorithm this thesis divide page into 6 groups and when proposed algorithm select victim page, it consider reference page frequency and page recency.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.434-441
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• 2001

The concept of network memory was introduced for the efficient exploitation of main memory in a cluster. Network memory can be used to speed up applications that frequently access large amount of disk data. In this paper, we present a memory a management algorithm that does not require prior knowledge of access patterns and that is practical to implement under the web server cluster, In addition, our scheme has a good user response time for various access distributions of web documents. Through a detailed simulation, we evaluate the performance of our memory managment algorithms.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.137-147
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• 2021

We aimsto examine the determinants of visitors' positive word-of-mouth (WOM) in a web-based virtual reality contemporary art exhibition. We also examines the effects of 3 realms of experience (entertainment, esthetic, escapist) on emotional arousal, how this emotional arousal affects memory and positive word-of-mouth, how memory affects positive word-of-mouth and how age moderate all of the paths. We examined a total of 297 visitors and was conducted through an online survey focusing on Chinese users of ages 20-49. The analysis results showed that entertainment and esthetic have an effect on emotional arousal, but escapist did not. The results also showed emotional arousal has an effect on memory and positive WOM. Memory did not affect positive word-of-mouth. Finally, age has a moderate effect on all the paths, except for the path form escape towards emotional arousal and memory to positive word-of-mouth. The theoretical implications of this study are meaningful exhibition research. While, it also will be helpful to segment the web-based virtual reality art exhibition visitors by dividing into 3 groups (20s, 30s, 40s) and to provide marketing and operation strategies.

• IE interfaces
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• v.20 no.2
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• pp.227-234
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• 2007

The national product identifier(NPI) currently used in the national product asset management system does not accommodate ISO or EPC standards due to the limitation of tag memory. For this reason, we propose a new NPI which accommodates not only ISO item identification standards but also the memory capacity of ISO tags. First of all, memory structures of ISO/IEC 18000-6C and EPC tags are analyzed from the view point of product identifier structure. Second, ISO/IEC 15459 and EPC identification standards as item identifier structures for the product asset management are analyzed. Third, based on these analyses, the NPI used for the current RFID-based product asset management system is analyzed and its problems are presented. Finally, a new NPI structure is proposed suitable for ISO/IEC 18000-6C and ISO/IEC 15459.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.164-170
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• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• Journal of Information Technology Applications and Management
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• v.11 no.1
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• pp.189-200
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• 2004

Recently Flash Memory which is small and low-powered is widely used as a storage of embedded system, because an embedded system requests portability and a fast response. To resolve a difference of access time between a storage and RAM, Linux is using disk caching which copies a part of file on disk into RAM. It is not also an exception on embedded system. A READ access-time of flash memory is similar to RAMs. So, when a process on an embedded system reads data, it is similar to the time to access cached data in RAM and to access directly data on a flash memory. On the embedded system using limited memory, using a disk cache is that wastes much time and memory spaces to manage it and can not reflects the characteristic of a flash memory. This paper proposes the regular file access of limited using a page cache in the file system based on a flash memory and reflects the characteristic of a flash memory. The proposed algorithm minimizes power consumption because access numbers of the RAM are reduced and doesn't waste a memory space because it accesses directly to a flash memory Therefore, the performance improvement of the system applying the proposed algorithm is expected.