• Title/Summary/Keyword: Memory grouping

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Real-time Garbage Collection Algorithm for Efficient Memory Utilization in Embedded Device (내장형 장비용 자바 가상 기계에서의 실시간 쓰레기 수집기 알고리즘에 관한 연구)

  • Choi, Won-Young;Park, Jae-Hyun
    • Proceedings of the KIEE Conference
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    • 1998.11b
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    • pp.672-674
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    • 1998
  • Java virtual machine has the garbage collector that automate memory management. Mark-compact algorithm is one of the garbage collection algorithm that operating in 2 phases, marking and sweeping. One is Marking is marking live objects reachable from root object set. Sweeping is sweeping unmarked object from memory(return to free memory pool). This algorithm is easy to implement but cause a memory fragmentation. So compacting memory, before memory defragmentation become serious. When compacting memory, all other processes are suspended. It is critical for embedded system that must guarantee real-time processing. This paper introduce enhanced mark-compact garbage collection algorithm. Grouping the objects by their size that minimize memory fragmentation. Then apply smart algorithm to the grouped objects when allocating objects and compacting memory.

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An Efficient Repair Method to Reduce Area Overhead by Sharing Bitmap Memory (비트맵 메모리 공유를 통해 면적을 크게 줄인 효율적인 수리 방법)

  • Cho, Hyungjun;Kang, Sungho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.237-243
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    • 2012
  • In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

A Memory-Efficient VLC Decoder Architecture for MPEG-2 Application

  • Lee, Seung-Joon;Suh, Ki-bum;Chong, Jong-wha
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.360-363
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    • 1999
  • Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

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A High-speed IP Address Lookup Architecture using Adaptive Multiple Hashing and Prefix Grouping (적응적인 복수 해슁과 프리픽스그룹화를 이용한 고속 IP 주소 검색 구조)

  • Park Hyun-Tae;Moon Byung-In;Kang Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.5 s.347
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    • pp.137-146
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    • 2006
  • IP address lookup has become a major bottleneck of packet forwarding and a critical issue for high-speed networking techniques in routers. In this paper, we propose an efficient high-speed IP address lookup scheme using adaptive multiple hashing and prefix grouping. According to our analysis results based on routing data distributions, we grouped prefix lengths and selected the number of hash functions in each group adaptively. As a result, we can reduce collisions caused by hashing. Accordingly, a forwarding table of our scheme has good memory efficiency, and thus is organized with the proper number of memory modules. Also, the proposed scheme has the fast building and searching mechanisms to develop the forwarding table only during a single memory access.

An efficient recognition of round objects using the curve segment grouping (곡선 조각의 군집화에 의한 둥근 물체의 효과적인 인식)

  • 성효경;최흥문
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.9
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    • pp.77-83
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    • 1997
  • Based on the curve segment grouping, an efficient recognition of round objects form partially occuluded round boundaries is proposed. Curve segments are extracted from an image using a criterion based on the intra-segment curvature and local contrast. During the curve segment extraction the boundaries of pratially occluding and occuluded objects are segmented to different curve segments. The extracted segments of constant intra-segment curvature are grouped to different curve segments. The extracted segments of constant intra-segment curvature are grouped nto a round boundary by the proposed grouping algorithm using inter-segment curvature which gives the relatinships among the curve segments of the same round boundary. The 1st and the 2nd order moments are used for the parameter estimation of the best fitted ellipse with round boundary, and then recognition is perfomed based on the estimated parameters. The proposed scheme processes in segment unit and is more efficient in computational complexity and memory requirements those that of the conventional scheme which processed in pixel units. Experimental results show that the proposed technique is very efficient in recognizing the round object sfrom the real images with apples and pumpkins.

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A Very Efficient Redundancy Analysis Method Using Fault Grouping

  • Cho, Hyungjun;Kang, Wooheon;Kang, Sungho
    • ETRI Journal
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    • v.35 no.3
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    • pp.439-447
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    • 2013
  • To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree-based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.

A Parallel Multiple Hashing Architecture Using Prefix Grouping for IP Address Lookup (프리픽스 그룹화를 이용한 병렬 복수 해슁 IP 주소 검색 구조)

  • Kim Hye ran;Jung Yeo jin;Yim Chang boon;Lim Hye sook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3B
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    • pp.65-71
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    • 2005
  • The primary function of the Internet routers is to forward incoming packets toward their final destinations. IP address lookup is one of the most important functions in evaluating router performance since IP address lookup should be performed in wire-speed for the hundred-millions of incoming packets per second. With CIDR, the IP prefixes of routing table have arbitrary lengths, and hence address lookup by exact match is no longer valid. As a result, when packets arrive, routers compare the destination IP addresses of input packets with all prefixes in its routing table and determine the most specific entry among matching entries, and this is called the longest prefix matching. In this paper, based on parallel multiple hashing and prefix grouping, we have proposed a hardware architecture which performs an address lookup with a single memory access.

Construction of Two-Class Classifier based on D1-MACA with minimum memory (D1-MACA 기반의 최소 메모리량을 갖는 두 패턴 분류기의 구성)

  • Hwang, Yoon-Hee;Cho, Sung-Jin;Choi, Un-Sook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.5
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    • pp.931-936
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    • 2009
  • Classification problem plays a major role in grouping of the records in database systems, detection of faults in VLSI circuits, image processing, and so on. In this paper, we propose the algorithm constructing D1-MACA as a two-class classifier with minimum memory for given pattern sets using the concepts of subspace. Also we analyze the condition that is designed a two-class classifier D1-MACA with two attractors.

A Design of SSD Dedicated RAID System for Efficient Resource Management (효율적인 자원관리를 위한 SSD 전용 RAID 시스템 설계)

  • Hyun-Seob Lee
    • Journal of Internet of Things and Convergence
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    • v.10 no.2
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    • pp.109-114
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    • 2024
  • Enterprise storage systems that require high data reliability are applying RAID (Redundant Array of Independent Disks) systems to recover from data loss and failure. In particular, RAID 5 ensures space efficiency and reliability by distributing parity across multiple storage devices. However, when storage devices have different capacities, RAID is built based on the smallest capacity storage device, resulting in wasted storage space. Therefore, research is needed to solve this resource management problem. In this paper, we propose a method for RAID grouping of each independent NAND flash memory block in a RAID consisting of SSD (Solid State Disk) with external SSDs as well as internal SSDs. This method is divided into a policy for delivering block information inside SSDs to the RAID system and a policy for RAID grouping of physical addresses delivered from the RAID system. This method allows us to maintain a RAID that does not waste resources when SSDs of different capacities are grouped into RAID5. Finally, we demonstrate the effectiveness of the proposed method through experiments.

Efficient Processing of Grouped Aggregation on Non-Uniformed Memory Access Architecture (비균등 메모리 접근 구조에서의 효율적인 그룹화 집단 연산의 처리)

  • Choe, Seongjun;Min, Jun-Ki
    • Database Research
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    • v.34 no.3
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    • pp.14-27
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    • 2018
  • Recently, to alleviate the memory bottleneck problme occurred in Symmetric Multiprocessing (SMP) architecture, Non-Uniform Memory Access (NUMA) architecture was proposed. In addition, since an aggregation operator is an important operator providing properties and summary of data, the efficiency of the aggregation operator is crucial to overall performance of a system. Thus, in this paper, we propose an efficient aggregation processing technique on NUMA architecture. Our proposed technique consists of partition phase and merge phase. In the partition phase, the target relation is partitioned into several partial relations according to grouping attribute. Thus, since each thread can process aggregation operator on partial relation independently, we prevent the remote memory access during the merge phase. Furthermore, at the merge phase, we improve the performance of the aggregation processing by letting each thread compute aggregation with a local hash table as well as avoiding lock contention to merge aggregation results generated by all threads into one.