• 대한전기학회논문지
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• 제40권7호
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• pp.718-724
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• 1991

In this paper, we proposed an algorithm to improve the memory efficiency by means of learning thresholds in spite of correlations among input patterns to be memorized. The proposed algorithm does not need preprocess correlations among input patterns but processes them with a threshold on a neural network. When memory contents are destroyed by correlation, nearly all patterns can be properly recovered with past learning. Through experiments we show how out algorithm can improve the memory efficiency.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2009년도 IWAIT
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• 생물정신의학
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• 제12권2호
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• pp.207-215
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• 2005

Objectives:This study was to compare verbal memory ability among patients with schizophrenia, bipolar manic patients and unipolar depressive patients, and to understand their charicteristics of memory process. Methods:All subjects were hospitalized patients and had been interviewed by using the Structured Clinical Interview for DSM-IV(SCID). Schizophrenic patients(N=40), bipolar manic patients(N=17), and unipolar depressive patients(N=20) were assessed with K-AVLT for verbal memory and with K-WAIS for verbal IQ. Three groups were compared regarding total immediate recall, delayed recall, delayed recognition, learning curve, memory retention, and retrieval efficiency under controlled verbal IQ. Multiple regression analysis was performed to find which clinical factors have an influence on verbal memory ability. Results:In MANCOVA, differences of verbal memory test scores among the groups were statistically significant(F=1.800, p<.05). In post hoc analysis, Patients with schizophrenia and bipolar mania showed poorer performance in immediate recall, delayed recall, delayed recognition, retrieval efficiency than unipolar depres- sive patients. And schizophrenics performed poorly in delayed recall, delayed recognition, retrieval efficiency than nonpsychotic affective disorder group, but no difference in total immediate recall, delayed recall, delayed recognition, retrieval efficiency between the schizophrenic group and the psychotic affective group. Conclusions:These results partially confirm previous reports of verbal memory ability among major psychiatric disorders. Our results showed that psychotic symptoms were related with verbal memory, and longer duration of illness was related with poorer performance in schizophrenia and unipolar depression.

• ETRI Journal
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• 제33권2호
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• pp.230-239
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• 2011

Dynamic memory allocators for real-time embedded systems need to fulfill three fundamental requirements: bounded worst-case execution time, fast average execution time, and minimal fragmentation. Since embedded systems generally run continuously during their whole lifetime, fragmentation is one of the most important factors in designing the memory allocator. This paper focuses on minimizing fragmentation while other requirements are still satisfied. To minimize fragmentation, a part of a memory region is segregated by the proposed budgeting method that exploits the memory profile of the given application. The budgeting method can be applied for any existing memory allocators. Experimental results show that the memory efficiency of allocators can be improved by up to 18.85% by using the budgeting method. Its worst-case execution time is analyzed to be bounded.

• International Journal of Internet, Broadcasting and Communication
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• 제14권1호
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• pp.188-193
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• 2022

The energy efficiency of memory systems is an important task in designing future computer systems as memory capacity continues to increase to accommodate the growing big data. In this article, we present an energy-efficient last-level cache management policy for future mobile systems. The proposed policy makes use of low-power PCM (phase-change memory) as the main memory medium, and reduces the amount of data written to PCM, thereby saving memory energy consumptions. To do so, the policy keeps track of the modified cache lines within each cache block, and replaces the last-level cache block that incurs the smallest PCM writing upon cache replacement requests. Also, the policy considers the access bit of cache blocks along with the cache line modifications in order not to degrade the cache hit ratio. Simulation experiments using SPEC benchmarks show that the proposed policy reduces the power consumption of PCM memory by 22.7% on average without degrading performances.

• 디지털산업정보학회논문지
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• 제5권3호
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• pp.59-67
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• 2009

This paper proposes a improved bitmap routing protocol, which finds the best energy efficient routing path by minimizing the network overheads and prolongs the overall network lifetime. Jung proposed a bitmap scheme for sensor networks. His scheme uses a bitmap table to represent the connection information between nodes. However, it has a problem that the table size is depends on the number of nodes in the sensor networks. The problem is very serious in the sensor node with a limited memory. Thereby, this paper proposes a improved bitmap routing protocol to solve the problem in Jung's scheme. Proposed protocol over the memory restricted sensor network could optimize the size of bitmap table by applying the deployed network property. Proposed protocol could be used in the diversity of sensor networks due to it has minimum memory overheads.

• ETRI Journal
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• 제32권4호
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• 아태비즈니스연구
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• 제11권4호
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• pp.255-269
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• 2020

Purpose - This paper analyzes the market efficiency focusing on the long memory properties of the domestic futures market. By decomposing futures prices into yield and volatility and looking at the long memory properties of the time series, this study aims to understand the futures market pricing and change behavior and risks, specifically and in detail. Design/methodology/approach - This study analyzes KOSPI 200 futures, KOSDAQ 150 futures, 3 and 10-year government bond futures, US dollar futures, yen futures, and euro futures, which are among the most actively traded on the Korea Exchange. To analyze the long memory and market efficiency, we used the Variance Ratio, Rescaled-Range(R/S), Geweke and Porter-Hudak(GPH) tests as semi- parametric methods, and ARFIMA-FIGARCH model as the parametric method. Findings - It was found that all seven futures supported the efficiency market hypothesis because the property of long memory turned out not to exist in their yield curves. On the other hand, in futures volatility, all 7 futures showed long memory properties in the analysis, which means that if new information is generated in the domestic futures market and the market volatility once expanded due to the impact, it does not decrease or shrink for a long period of time, but continues to affect the volatility. Research implications or Originality - The results of this paper suggest that it can be useful information for predicting changes and risks of volatility in the domestic futures market. In particular, it was found that the long memory properties would be further strengthened in the currency futures and bond rate futures markets after the global financial crisis if the regime changes of the domestic financial market are taken into account in the analysis.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제20권9호
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• pp.483-491
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• 2014

현대의 컴퓨터 시스템에서는 동적 전압/주파수 조정(DVFS: Dynamic Voltage/Frequency Scaling) 기법을 이용하여 성능과 전력 소모의 균형을 이루도록 한다. DVFS 정책의 유용성은 높아진 주파수에 따른 소모 전력에 대한 성능 향상 정도에 달려있다. 특히 메모리 I/O가 많은 응용의 경우 CPU 주파수 상승에 비례하여 성능이 향상되지 않는 경우가 많다. 본 논문에서는 메모리 접근 빈도에 기반하여 CPU 주파수 조정의 상한을 결정하도록 하였다. 명령어 당 메모리 접근(최종 수준 캐시 미스) 빈도에 따라 CPU 주파수 상향으로 인한 성능 향상이 제한되는 것을 실험으로 확인하고, 성능 향상의 이득이 작아지는 CPU 주파수를 제시하도록 한다. 본 논문의 기법을 적용한 실험 결과는 메모리 접근 빈도가 높은 응용에 대하여 30% 이상의 에너지 효율 상승이 있음을 보인다.

• Journal of Web Engineering
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• 제20권6호
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• pp.1813-1828
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• 2021

In a computing environment, higher resolutions generally require more memory bandwidth, which inevitably leads to the consumption more power. This may become critical for the overall performance of mobile devices and graphic processor units with increased amounts of memory access and memory bandwidth. This paper proposes a lossless compression algorithm with a multiple differential pulse-code modulation variable sign code Golomb-Rice to reduce the memory bandwidth requirement. The efficiency of the proposed multiple differential pulse-code modulation is enhanced by selecting the optimal differential pulse code modulation mode. The experimental results show compression ratio of 1.99 for high-efficiency video coding image sequences and that the proposed lossless compression hardware can reduce the bus bandwidth requirement.