• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1068-1074
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• 2010

In high speed railway, event recorder is essential system for analyzing the cause of train accident. It stores train operation sent by train control system in safe memory unit. Crash protected memory, the safe memory unit for event recorder, keeps the stored contents from severe environment. For crash protected memory, we have designed the architecture of concrete enclosure and controller board. Proposed system provides large volume of memory capacity and fault tolerance architecture. For checking the characteristics of proposed crash protected memory specification, the simulation is executed. Simulation results shows the designed crash protected memory meets all requirements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.2 s.95
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• pp.15-22
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• 1999

This paper demonstrates the feasibility of Shape Memory Alloy (SMA) actuators in controlling the motion of micro active catheter. The dynamic behavior of SMA is obtained by several experiments for the design of the controller. With the control parameters obtained in experiments, temperature feedback control algorithm is proposed and realized. The prototype of micro active catheter is fabricated, and its control performance which uses the designed controller is investigated. The results obtained show the potential of the SMA as viable means for actuating the micro active catheter.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.1
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• pp.263-270
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• 1995

The use of the shape memory alloy, Nitinol wire, is investigated as an actuator for enhancing the damping in structural vibration systems. The first-order mathematical model of the Nitinol wire is obtained from the experimental data for an actuator. Finite element method is utilized for the strain gage sensor model, which is installed at the root of cantilever beam. A simple system, cantilever beam, is built as a flexible structural system to implement a control law with the Nitinol wire actuator. The system model including sensor and actuator is derived, which agrees with the experimental results. The actuator dynamics is augmented with the system so as to design PI controller and the one of robust controllers, LQG/LTR controller, and the control laws are implemented experimentally. The experimental study shows the feasibility of utilizing the Nitinol wire as an actuator for the purpose of vibration control.

• ETRI Journal
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• v.32 no.1
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• pp.84-92
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• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.521-527
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• 2011

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME. Therefore this study suggests the electrically optimum Interface matching, Artwork technology based on the signal cross over and PCB stacking method on the harsh environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.768-771
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• 2007

Recently, Nand flash memory is widely used for digital equipments and its capacity and performance are rapidly improving. The limit on the number of writings and readings to/from Nand flash memory does not guarantee the integrity of its data. Therefore, ECC algorithm should be applied to the Nand flash controller. To reduce the access time, we use the look-up table to implement the ECC algorithm instead of the conventional logic gates.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.11
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• Journal of the Korean Society for Precision Engineering
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• v.12 no.9
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• pp.167-174
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• 1995

This paper experimentally demonstrates the feasibility of using shape memory alloy(SMA) actuators in controlling structural vibrations of a flexible cantilevered beam. The dynamic characteristics of the SMA actuator are identified and integrated with the beam dynamics. Three types of control schemes; constant amplitude controller(CAC), proportional amplitude controller (PAC) and sliding mode controller(SMC) are designed. The CAC and PAC are determined on the basis of physical phenomenon of the SMA actuator, while teh SMC is formulated in a mathematical manner. The proposed controllers are implemented and evaluated at various operating condirions by investigating the control level of suppression in transient vibration.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.