• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.4
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• pp.747-754
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• 2013

This study introduces a recently designed desktop-sized NC turning system and its components. This machine is designed for the ultra-precise turning of parts with a diameter of 0.5-20 mm with minimum space usage for the machine. This study aims to achieve submicron-level accuracy of movements and good rigidity of the machine for precision machining using the desktop-sized machine. The components such as the main machine structure, air bearing servo spindle, and XZ stage with needle roller guides are designed, and the designed machine is built with a PC-based CNC controller. Its static and dynamic stiffness performances and positioning resolutions are tested. Through machining tests with single-crystal diamond tools, a form error less than $0.8{\mu}m$ and surface roughness (Ra) of $0.03{\mu}m$ for workpieces are obtained.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.35-42
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• 2003

We have studied DC energy conversion of RF card by wireless communication. In order to attain an objective, it used the system which is a Rectenna. The main purpose of energy conversion system is the operation of the circuits at RF-ID system. The proposed RF-ID system is a lot classified with the reader and tag. Reader is a kind of the base station role supporting RF energy. And priority tag convert RF energy from the reader it was delivered with a wireless to DC energy. The energy which is converted like Tag. It transmits to the reader characteristic ID of each card. The tag is mainly divided into rectifier, power module, memory and controller. The FRAM maintains the data like a ROM in no-power situation. And the advantage is a low power element compared with other EEPROM. There are two considerations, when RF energy is converted into DC source by wireless. One is energy amount supported from the reader, the other is high power efficiency. This paper presents a study of simulation and experiments on the RF-DC conversion circuit in tag by the power efficiency concentrated.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3423-3438
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• 2014

In recent years, wearable sensor devices are reshaping the way people live, work, and play. A wearable sensor device is a computer that is subsumed into the personal space of the user, and is always on, and always accessible. Therefore, among the most salient aspects of a wearable sensor device should be a small form factor, long battery lifetime, and real-time characteristics. Thereby, sophisticated applications of a wearable sensor device use real-time operating systems to guarantee real-time deadlines. The deterministic multi-dimensional task scheduling algorithms are implemented on ARC (Actual Remote Control) with relatively limited hardware resources. ARC is a wearable wristwatch-type remote controller; it can also serve as a universal remote control, for various wearable sensor devices. In the proposed algorithms, there is no limit on the maximum number of task priorities, and the memory requirement can be dramatically reduced. Furthermore, regardless of the number of tasks, the complexity of the time and space of the proposed algorithms is O(1). A valuable contribution of this work is to guarantee real-time deadlines for wearable sensor devices.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.139-147
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• 2017

In recent years, non-volatile memory express (NVMe), a new host controller interface standard, has been adapted to overcome performance bottlenecks caused by the acceleration of solid state drives (SSD). Recently, performance breakthrough cases over AHCI based SATA SSDs by adapting NVMe based PCI Express (PCIe) SSD to servers and PCs have been reported. Furthermore, replacing legacy eMMC-flash storage with NVMe based storage is also considered for next generation of mobile devices such as smartphones. The Linux kernel includes drivers for NVMe support, and as the kernel version increases, the implementation of the NVMe driver code has changed. However, mobile devices are often equipped with older versions of Android operating systems (OSes), where the newest features of NVMe drivers are not available. Therefore, different features of different NVMe driver implementations are not well evaluated on Android OSes. In this paper, we analyze the response time of the NVMe driver for various Linux kernel version.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.10 no.1
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• pp.95-105
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• 2006

The speed of hard disk which is based on mechanical operation is more slow than processor. The growth of processor speed is rapid by semiconductor technology, but the growth of disk speed which is based on mechanical operation is not enough. Buffer cache in main memory and disk cache in disk controller have been used in computer system to solve the speed gap between processor and I/O subsystem. In this paper, an efficient buffer cache and disk cache management scheme was proposed to restrict duplicated disk block between buffer cache and disk cache. The performance of the proposed algorithm was evaluated by simulation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.295-296
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• 2006

We developed wire frame drive unit based on SMA for the 3D Shape display. Our basic concept is wire frame combination connected with a chain form which can create various shapes and it compared with pin array mechanism which is not able to display mushroom shape. It imitates antagonist mechanism of human musculoskeletal system. we create similar motion using repair-relaxation mechanism and locking mechanism by SMA. Therefore, in this paper, we propose SMA control solution for actuating repair-relaxation mechanism and locking mechanism. In our control system. we use optical sensor and quantitative angle between wire frames for closed loop control. And we supply amplified current for SMA by circuit composed of transistor and apply PWM signal to circuit for efficient control. So, wire frame drive unit enable diversity angle control based on sensor data. And then combination of wire frame drive units will create various objects.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.5
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• pp.36-42
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• 1980

In this study, multi-microprocessors system in which slave microprocessor is conrlected with master microprocessor bus through the DMA controller is designed by the use of four 8085 CPU. A high degree of processing efficiency could be obtained by making this system work parallel processing. The result of measuring relat ions bet ween working microproressor and system throughput was 70-80 percents lower than ideal value Master microprocessor takes charge of resource allocation and scheduling, common memory assigns communication between microprocessors and a store of common data. The met hod of detecting Pa rallelism from source Program composed by series is also suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.