• 디지털산업정보학회논문지
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• 제12권4호
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.216-220
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• 1987

A graphic display and operator console system is developed for monitoring the operation of power plant. It has multiprocessor structure using VME bus and common memory. The graphic monitoring system is applied to fault tolerant control system for enhancing reliability of boiler analog controller. As a result, it displays all the operating date as color graphic images with 14 pages. Moreover, it can transfer the operator commands to the other micro-processors through common memory.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 A
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• pp.492-494
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• 1993

CMAC (Cerebeller Model Articulation Controller) is kind of Neural Networks that imitate the human cerebellum. For storage and retrieval of learned data, the input of CMAC is used as a key to determine the memory location. he learned information is distributively stored in physical memory. The learning of CMAC is very fast and converged well, therefore, it effects the application of Pattern Recognition. Through the our experiment of Pattern Recognition, we will prove that CMAC is very suitable for On-line real time processing and incremental learning of Neural Networks.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 춘계학술발표회논문집(1)
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• pp.349-354
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• 1996

SACOM(Simulation Analyser with Cognitive Operator Model) is being developed at Korea Atomic Energy Research Institute to simulate human operator's cognitive characteristics during the emergency situations of nuclear power plans. An operator model with error mechanisms has been developed and combined into SACOM to simulate human operator's cognitive information process based on the Rasmussen's decision ladder model. The operational logic for five different cognitive activities (Agents), operator's attentional control (Controller), short-term memory (Blackboard), and long-term memory (Knowledge Base) have been developed and implemented on blackboard architecture. A trial simulation with a scenario for emergency operation has been performed to verify the operational logic. It was found that the operator model with error mechanisms is suitable for the simulation of operator's cognitive behavior in emergency situation.

• 한국정밀공학회지
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• 제13권8호
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• pp.155-163
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• 1996

This paper presents vibration and position tracking control of a smart structure using shape memory alloy(SMA) actuators. A governing equation of motion of the proposed structure is obtained via Hamilton's princeple. The dynamic characteristics of the SMA actuator are experimentally identified and incorporated with the governing equation to furnish a control system model. Subsequently, a sliding mode controller which has inherent robustness to external disturbances is formulated on the basis of the sliding mode conplacement, and also for the position tracking control of desired trajectories with low-frequency sine and square waves.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• 한국항공우주학회지
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• 제36권8호
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• pp.816-823
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• 2008

본 논문에서는 Xilinx GTP 인터페이스와 DDR-2 메모리를 이용하여 개발된 고속 데이터 처리 유닛의 시험 결과를 제시하였다. 고속 데이터 처리 유닛은 1.25Gbps로 수신된 데이터를 메모리에 저장하며 이 데이터는 다시 700Mbps로 수신 저장 시스템으로 전송된다. 따라서 고속의 데이터 처리를 위해서 CPU 대신에 FPGA가 직접 메모리를 읽고 쓸 수 있도록 DDR-2 메모리 제어기를 구현 하였다.

• 디지털콘텐츠학회 논문지
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• 제18권7호
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• pp.1451-1456
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• 2017

본 연구에서는 형상기억합금(SMA)을 응용한 스마트 액추에이터의 효율적 제어를 위한 통합 액추에이터-제어기 시스템 설계를 논의한다. 이를 위하여 두 개의 스마트 SMA 액추에이터 유닛과 함께 제어를 위한 싱글 칩 마이크로프로세서, 액추에이터 드라이버, 센서를 통합한 새로운 액추에이터-제어기 모듈을 설계하고 제작하였다. 제안된 시스템에서는 피드백 제어를 위해 모듈의 회전을 측정하는 6축 모션센서 칩과 SMA의 저항을 측정하는 회로를 포함한다. 실험을 통하여 액추에이터의 구동과 센서 신호와 통신을 확인하였고 이를 통하여 실제 액추에이터-제어기 시스템의 작동을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• 한국산업정보학회논문지
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• 제20권4호
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• pp.103-109
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• 2015

본 논문은 MCU에 내장된 플레쉬 메모리의 오동작 테스트를 shmoo 테스트 기법을 사용하고, 이 기능을 내장한 롬라이트 개발에 관한 논문이다. shmoo 테스트는 다양한 입력조건에 대한 응답을 도표로 나타내고 분석하는 기법으로, 마이크로프로세서, ASIC 및 메모리와 같은 집적회로 또는 컴퓨터 시스템의 성능분석의 기법으로 사용된다. 개발된 롬라이터는 Shmoo 검사를 수행하고 Flash 32K의 쓰기를 수행하였을 때 6.4s 정도의 시간이 소요되었으며, 이는 현재 사용하고 있는 ROM Writer의 속도에 비해 약 20% 정도 향상되었다.