• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1743-1744
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• 2006

기존의 89S51의 Flash Memory에 데이터를 저장하기 위해서 패러럴 포트를 사용하였다. 하지만 패러럴 포트를 이용한 방법은 많은 단점을 갖고 있는데, 그 중에 하나의 포트에 하나의 디바이스밖에 접속 할 수 없기 때문에 여러 디바이스를 접속하기 위해서는 포트 수를 증가시켜야 한다는 문제점이 있다. PC는 패러럴 포트를 $1{\sim}2$개 정도만 갖고 있어서 확장을 하기가 여의치 않다. 이에 따라 패러럴 포트의 단점을 보완하고자 한다. 이러한 문제를 해결하고 보완 할 수 있는 USB 통신을 이용해 Micro-Controller인 89S51에 내장된 Flash Memory에 데이터를 저장하려고 한다.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1254-1260
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• 2009

CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.533-543
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• 2008

With technological advances for storage volume size of a semiconductor memory, USB storage is made as products to support a high capacity storage. Hereby, consumers discard pint-sized USB storages which they already had, or do not use them efficiently. To integrate and unify these pint-sized USB storages as one big USB storage, we proposed Sigma Hub. It can be grouping multiple USB storages, which have each different volume size of memory storage, as logical unity Storage through USB Hub. The proposed Sigma Hub includes Sigma Controller as a core management module to unify the multiple USB storages in transaction level layer. Sigma controller can efficiently control transaction packet in Sigma Hub through a USB Storage-Integration algorithms which ensure an integrity for data read and write processes. Consequently, Sigma Hub enables the use of USB storage that is logical unity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.181-185
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• 2014

The lifetime of a solid-state drive (SSD) is limited because of the number of program and erase cycles allowed on its NAND flash blocks. Data cannot be overwritten in an SSD, leading to an out-of-place update every time the data are modified. This result in two copies of the data: the original copy and a modified copy. This phenomenon is known as write amplification and adversely affects the endurance of the memory. In this study, we address the issue of reducing wear leveling through efficient handling of write requests. This results in even wearing of all the blocks, thereby increasing the endurance period. The focus of our work is to logically divert the write requests, which are concentrated to limited blocks, to the less-worn blocks and then measure the maximum number of write requests that the memory can handle. A memory without the proposed algorithm wears out prematurely as compared to that with the algorithm. The main feature of the proposed algorithm is to delay out-of-place updates till the threshold is reached, which results in a low overhead. Further, the algorithm increases endurance by a factor of the threshold level multiplied by the number of blocks in the memory.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.444-446
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• 1994

This paper describes the design of a digital multifunction controller for the intelligent high voltage customer switchboard and proposes a relaying algorithm for high impedance faults using back-propagation neural network. The hardware design uses the three microprocessors and global memory architecture to achive real time operation and control 4 feeders. The controller uses a 64-point radix-4 DIF FFT algorithm to measure the harmonic and relay parameters. Synthesized fault current waveforms are used to train and test the back - propagation network.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1791-1794
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• 2006

For system-on-glass (SoG) with low-temperature poly-silicon (LTPS) thin film transistor (TFT), a new system interface architecture and timing controller are developed. With the newly developed system interface architecture, line memory can be eliminated which would take large area of SoG display panel. The system interface and timing controller are targeted for the application for 6-bit gray scale, 60-frames/s qVGA format.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.524-527
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• 1988

Basic types of bilateral servo systems were described and practical consideration in the bilateral servo controller design was introduced. Power assistance to the operator is essential for high efficiency and accurate force reflection is necessary for dexterous manipulation. This paper shows a controller structure under development at KIMM which employs nonlinear friction compensation and memory based gravity compensation technique for efficiency and dexterity.