• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.634-646
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• 2015

Coarse-Grained Reconfigurable Architecture (CGRA) is a very promising platform that provides fast turn-around-time as well as very high energy efficiency for multimedia applications. One of the problems with CGRAs, however, is application mapping, which currently does not scale well with geometrically increasing numbers of cores. To mitigate the scalability problem, this paper discusses how to use the SIMD (Single Instruction Multiple Data) paradigm for CGRAs. While the idea of SIMD is not new, SIMD can complicate the mapping problem by adding an additional dimension of iteration mapping to the already complex problem of operation and data mapping, which are all interdependent, and can thus significantly affect performance through memory bank conflicts. In this paper, based on a new architecture called SIMD reconfigurable architecture, which allows SIMD execution at multiple levels of granularity, we present how to minimize bank conflicts considering all three related sub-problems, for various RA organizations. We also present data tiling and evaluate a conflict-free scheduling algorithm as a way to eliminate bank conflicts for a certain class of mapping problem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.2
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• pp.140-145
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• 2013

This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

• Journal of KIISE
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• v.42 no.4
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• pp.442-450
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• 2015

This paper proposes a method for reducing false conflicts in signature-based eager hardware transactional memory (HTM). The method tracks the information on all cache blocks that are accessed by a transaction. If the information provides evidence that there are no conflicts for a given transactional request from another core, the method prevents the occurrence of a false conflict by forcing the HTM to ignore the decision based on the signature. The method is very effective in reducing false conflicts and the associated unnecessary transaction stalls and aborts, and can be used to improve the performance of the multicore processor that implements the signature-based eager HTM. When running the STAMP benchmark on a 16-core processor that implements the LogTM-SE, the increased speed (decrease in execution time) achieved with the use of the method is 20.6% on average.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• Cross-Cultural Studies
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• v.46
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• pp.199-225
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• 2017

Death and the Maiden(1990), by the Chilean playwright Ariel Dorfman, directly addresses the issue of liquidating the past that the transient democratic government of Patricio Aylwin faced, the government established right after the end of the dictatorship of Augusto Pinochet. This article focuses on analyzing the aspects of conflicts and discords between memories of individuals as reflected in the conversations between characters of the play. For example. we look into the effects of traumatic memories of Paulina, tortured and raped by the past government, on her everyday life and examine the relationship between her personal memory and the collective memory. We also look into the discourse of the dominating memory through the confession of the rapist doctor Roberto, and observe how Gerardo, a lawyer appointed as a member of the investigation committee, exposes the truth of the case and mediates the conflict of the memories between the two characters. We uncover the problems inherent in the state memory as it tries to intervene in the strife in memories between assailants and victims and explore the possibility that the concept of memory deterritorialization would be an alternative to overcome these problems.

• Journal of Digital Convergence
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• v.11 no.2
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• pp.287-297
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• 2013

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient "In-place" memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

• Science of Emotion and Sensibility
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• v.16 no.3
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• pp.341-350
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• 2013

The present study aimed to understand the sensory characteristic of change detection by comparing the experience of detecting a salient visual change against the experience of detecting a sensory conflict evoked by a binocular mismatch. In Experiment 1, we used the change detection task where 2, 4, or 6 items were short-term remembered in visual working memory and were compared with following test items. The half of change-present trials were manipulated to elicit a binocular rivalry on the test item with the change by way of monocular inputs across the eyes. The results showed that change detection accuracy without the rivalry manipulation declined evidently as the display setsize increased whereas no such setsize effect was observed with the rivalry manipulation. Experiment 2 tested search efficiency for the search array where the target was designated as an item with the rivalry manipulation, and found the search was very efficient regardless of the rivalry manipulation. The results of Experiment 1 and 2 showed that when the given memory load varies, the experience of detecting a salient visual change become similar to the experience of detecting a sensory conflict by a binocular rivalry.

• Journal of KIISE:Databases
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• v.29 no.6
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• pp.464-476
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• 2002

Main-memory database systems which reside entire databases in main memory are suitable for high-performance real-time transaction processing. If two-phase locking(2PL) as concurrency control protocol is used for the transactions accessing main-memory databases, however, the possibility of lock conflict will be low but lock operations become relatively big overhead in total transaction processing time. In this paper, We designed a real-time static locking(RT-SL) protocol which minimizes lock operation overhead and reflects the priority of transactions and we implemented it on a main-memory real-time database system, Mr.RT. We also evaluate and compare its performance with the existing real-time locking protocols based on 2PL such as 2PL-PI and 2PL-HP. The extensive experiments reveal that our RT-SL outperforms the existing ones in most cases.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1429-1436
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• 1999

데이타들에 대한 선인출 효과를 얻기 위하여 캐쉬 메모리의 캐쉬 블록은 다중 워드로 구성된다. 그러나 선인출된 데이타들이 사용되지 않을 경우 캐쉬 메모리가 낭비되고 따라서 캐쉬 실패율이 증가한다. 데이타 배열 병합 방법은 캐쉬 실패 원인의 하나인 캐쉬 충돌 실패를 감소시키기 위하여 사용되고 있다. 그러나 기존의 배열 병합 방법은 유용하지 못한 데이타들을 캐쉬 블록에 선인출하는 현상을 보인다. 본 논문에서는 이러한 현상을 개선한 스트라이드 배열 병합을 제안한다. 모의시험에서 캐쉬 블록이 다중 워드로 구성된 경우 스트라이드 배열 병합은 캐쉬 충돌 실패를 감소시킬 뿐 만 아니라 유용한 데이타 선인출을 증가 시키므로 캐쉬 성능을 향상시킴을 보여준다. 또한 이렇게 향상된 캐쉬 성능은 프로세서 증가에 따른 확장성 있는 프로그램 성능을 나타낸다.Abstract The cache memory is composed of cache lines with multiple words to achieve the effect of data prefetching. However, if the prefetched data are not used, the spaces of the cache memory are wasted and thus the cache miss rate increases. The data merging-arrays method is used for the sake of the reduction of the cache conflict misses. However, the existing merging-arrays method results in the useless data prefetching. In this paper, a stride merging-arrays method is suggested for improving this phenomenon. Simulation results show that when a cache line is composed of multiple words, the stride merging-arrays method increases the cache performance due to not only the reduction of cache conflict misses but also the useful data prefetching. This enhanced cache performance also represents the more scalable performance of parallel applications according to increasing the number of processors.

• Korean Journal of Cognitive Science
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• v.23 no.1
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• pp.25-46
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• 2012

When performing a monotonous task, one often experiences an urge to quit. This urge may vary depending on how long one has performed the task (a temporal factor) and on which particular component of the task one is carrying out (an event-based factor). Using the Stroop task and a working memory task, we examined changes in the urge to quit as a function of basic temporal (repetition) and event-based (cognitive conflict) factors. Consistent with the law of least work and recent theorizing, for the memory task, urges to quit were greater following difficult trials; for the Stroop task, urges to quit were greater following incongruent than congruent trials, but only during early/novice phases of performance, when responding is inefficient. This is a demonstration of an avoidance response toward cognitive conflict. Regarding temporal sources of quitting, urges to quit were greater for late task stages than early stages. These basic findings may illuminate the nature of the more 'hot' motivational struggles involving the delay of gratification.