• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1625-1635
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• 1997

An extension of the weighted buddy system, called the extended-weighted buddy system, for dynamic memory allocation in an object-oriented computer is presented. The extended-weighted buddy system allows block sizes of $2^k,\;3*2^k,\;5*2^k,\;7*2^k$, whereas the original weighted buddy system allowed block sizes of $2^k\;and\;3*2^k$. This extension is achieved at only the cost of additional 3 bits per block for memory management unit. Simulation results are presented which compare our method with the weighted buddy system. These results indicate that, for uniform request distributions, our system has less internal memory fragmentation than the weighted buddy system(approximately 60%). And, for exponential request distributions, it has less internal memory fragmentation than the weighted buddy method (approximately 50%). The external fragmentation is greater for this system than the weighted buddy system. But, our system has less total memory fragmentation for exponential request distributions, and two systems take a similar total memory fragmentation for uniform request distributions, so we can substitutes the extended-weighted buddy system for weighted buddy system.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.767-774
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• 2010

Due to advantages of NAND flash memory such as non-volatility, low access latency, low energy consumption, light weight, small size and shock resistance, it has become a better alternative over traditional magnetic disk drives, and has been widely used. Traditional DBMSs including mobile DBMSs may run on flash memory without any modification by using Flash Translation Layer (FTL), which emulates a random access block device to hide the characteristics of flash memory such as "erase-before-update". However, most existing FTLs are optimized for file systems, not for DBMSs, and traditional DBMSs are not aware of them. Also, traditional DBMSs do not consider the characteristics of flash memory. In this paper, we propose a flash-conscious storage system for DBMSs that utilizes flash memory as a main storage medium, and carefully put the characteristics of flash memory into considerations. The proposed flash-conscious storage system exploits log records to avoid costly update operations. It is shown that the proposed storage system outperforms the state.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• International Area Studies Review
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• v.14 no.2
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• pp.25-40
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• 2010

Accurate forecasting of volatility is of considerable interest in financial volatility research, particularly in regard to portfolio allocation, option pricing and risk management because volatility is equal to market risk. So, we attempted to delineate a model with good ability to forecast and identified stylized features of volatility, with a focus on volatility persistence or long memory in the Australian futures market. In this context, we assessed the long-memory property in the volatility of index futures contracts using three conditional volatility models, namely the GARCH, IGARCH and FIGARCH models. We found that the FIGARCH model better captures the long-memory property than do the GARCH and IGARCH models. Additionally, we found that the FIGARCH model provides superior performance in one-day-ahead volatility forecasts. As discussed in this paper, the FIGARCH model should prove a useful technique in forecasting the long-memory volatility in the Australian index futures market.

• Communications for Statistical Applications and Methods
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• v.24 no.5
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• pp.507-518
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• 2017

Volatility plays a crucial role in theory and applications of asset pricing, optimal portfolio allocation, and risk management. This paper proposes a combined model of autoregressive moving average (ARFIMA), generalized autoregressive conditional heteroscedasticity (GRACH), and skewed-t error distribution to accommodate important features of volatility data; long memory, heteroscedasticity, and asymmetric error distribution. A fully Bayesian approach is proposed to estimate the parameters of the model simultaneously, which yields parameter estimates satisfying necessary constraints in the model. The approach can be easily implemented using a free and user-friendly software JAGS to generate Markov chain Monte Carlo samples from the joint posterior distribution of the parameters. The method is illustrated by using a daily volatility index from Chicago Board Options Exchange (CBOE). JAGS codes for model specification is provided in the Appendix.

• 한국전산유체공학회:학술대회논문집
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• 2005.10a
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• pp.157-162
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• 2005

Parallel implementation and performance assessment of the grid assembly in a structured chimera grid approach is studied. The grid assembly process, involving hole cutting and searching donor, is parallelized on the PC cluster. A message passing programming model based on the MPI library is implemented using the single program multiple data(SPMD) paradigm. The coarse-grained communication is optimized with the minimized memory allocation because that the parallel grid assembly can access the decomposed geometry data in other processors by only message passing in the distributed memory system such as a PC cluster. The grid assembly workload is based on the static load balancing tied to flow solver. A goal of this work is a development of parallelized grid assembly that is suited for handling multiple moving body problems with large grid size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.80-90
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• 2016

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.228-231
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• 2008

For a satellite data communication, the technology of frame synchronization is widely used between a sender and a receiver. Last year, we suggested zero-loss frame synchronization [1] using pattern search and using bits threshold search algorithm that is based on SIMD technology [2,3]. This algorithm could solve both of hardware and software drawbacks, which are frame loss and low processing performance. However, this algorithm didn't optimize the processing of output data, synchronized data, which caused overhead to the memory allocation and the memory copy. Consequently, the performance of the frame synchronizer application was degraded. In this paper, we enhance previous work using a circular buffer in order to optimize the output data processing. The performance comparison with the previous algorithm shows that the enhanced proposed approach dramatically outperforms in the output data processing speed.

• The Journal of Information Technology
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• v.5 no.2
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• pp.27-34
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• 2002

The KVM garbage collector implemented in CLDC was generally based on the simple mark-sweep algorithm, but it is difficult to handle objects of varying size without fragmentation of the available memory. In this paper, we have designed and implemented a memory allocator based on the mark-sweep algorithm that minimizes the fragmentation by the method that determines the allocation position of free-space list according to object size. The experimental result shows that our algorithm reduce the fragmentation and improve the execution time than the existing algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.232-234
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• 2003

자바가상기계는 힙 영역과 자바 스택 영역에 객체와 스택 프레임을 할당할 공간이 없을 때 가비지 콜렉션과 함께 이미 해제된 힙과 자바 스택 영역을 재사용 가능하도록 메모리 공간을 재구성하게 된다. 한편 메모리 단편화로 인해 객체 또는 스택 프레임을 더 이상 할당하지 못하는 경우 자바가상기계는 컴펙션을 수행하여 메모리 단편화를 제거하면서 메모리를 재구성한다. 하지만 자바가상기계에서 메모리 재구성은 가비지 콜렉션및 컴펙션과 함께 길고 예측할 수 없는 지연시간에 의해 내장형 자바가상기계의 성능을 저하시키는 단점을 가진다. 본 논문은 소규모 내장형 자바가상기계의 성능을 개선하기 위한 방안으로, 가변 크기를 가지는 객체와 스택 프레임을 고정 크기로 변환하여 메모리를 할당하는 고정 크기 메모리 할당에 대해 기술하고 있다. 고정 크기 메모리 할당은 메모리 전체 사용율은 떨어지지만 외부 단편화가 발생하지 않기 때문에 회수된 메모리 공간을 재구성하지 않고도 힙 영역과 자바 스택 영역에 객체와 스택 프레임을 할당 가능하다. 본 논문에서 기술한 고정 크기 메모리 할당 방식으로 객체와 스택 프레임을 할당하게 되면 가변 크기 메모리 할당 보다 약 10% ~ 30% 효율향상을 보였다.