• 제목/요약/키워드: Memory Test

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Parallel Testing Circuits with Versatile Data Patterns for SOP Image SRAM Buffer (SOP Image SRAM Buffer용 다양한 데이터 패턴 병렬 테스트 회로)

  • Jeong, Kyu-Ho;You, Jae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제46권9호
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    • pp.14-24
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    • 2009
  • Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

Design of the Memory Error Test Module at a Device Driver of the Linux (리눅스 디바이스 드라이버 내의 메모리 오류 테스트 모듈 설계)

  • Jang, Seung-Ju
    • The KIPS Transactions:PartA
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    • 제14A권3호
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    • pp.185-190
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    • 2007
  • The necessity of error test module is increasing as development of embedded Linux device driver. This paper proposes the basic concept of freed memory error test module in the Linux device driver and designs error test module. The USB device driver is designed for freed memory error test module. I insert the test code to verify the USB device driver. I test the suggested error test module for the USB storage device driver. I experiment error test in this module.

Effects of Combat Related PTSD on Memory Function : in Vietnam Veterans (월남전 참전 재향군인들에서 외상 후 스트레스 장애가 기억기능에 미치는 영향)

  • Woo, Deuk-Ku;Kang, Hyun-Sook;Choi, Young-An
    • Korean Journal of Psychosomatic Medicine
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    • 제6권2호
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    • pp.136-146
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    • 1998
  • Objectives : This study was performed to evaluate the effects of PTSD on memory function, to investigate the difference of memory function between PTSD and non-PTSD patients, and to identify major variables correlated to PTSD scale and Memory Assessment Scale. Methods: The authors used PTSD-scale(Mississippi scale and Combat Exposure Scale) for measuring PTSD severity. And, Beck Depression Inventory was also used. Memory assessment scale was assessed by well trained psychologist. Thirty one Vietnam veterans who had been hospitalized were collected consecutively. These patients were evaluated by psychiatrists with interview and measurement for fifteen months since March, 1997. The collected data were analyzed by SPSS and the stastistic methods used for analysis Chi-square, t-test, and Pearson's correlation. Results : 1) There were significant differences in short-term memory and verbal memory between PTSD and non-PTSD in Vietnam veterans. 2) Mississippi scale and Combat Exposure Scale were negatively correlated to short-term memory and verbal memory(Pearson's correlation). 3) Religion status was a significant variable between PTSD and non-PTSD in Vietnam veterans. 4) There is no significant difference in visual memory and total memory scale between PTSD and Non-PTSD in Vietnam veterans Conclusions : Neuropsychological changes were found in the posttraumatic stress disorder. There were significant differences in short-term memory and verbal memory between PTSD and non-PTSD in Vietnam veterans. Mississippi scale and Combat Exposure Scale were negatively correlated to short-term memory and verbal memory. We suggest that neuropsychological test might be used for an objective assessment of patients with the combat related PTSD and be considered helpful in the assessment of patients with the diagnosis. And we also suggest rehabilitation strategies would be used to compensate for memory deficits in PTSD patients.

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The Experimental Study on the Effects of Hangbujapalmultang on Enhancing Learning and Memory in Rats with Radial Arm Maze (향부자팔물탕(香附子八物湯)이 흰쥐의 방사형 미로학습(迷路學習)과 기억(記億)에 미치는 영향(影響))

  • Ryu Jae-Myun;Kim Jong-Woo;Whang Wei-Wan;Kim Hyun-Taek;Lee Hong-Jae
    • Journal of Oriental Neuropsychiatry
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    • 제9권2호
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    • pp.45-51
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    • 1998
  • Purpose : This study has an experiment on finding how Hyangbujapamultang advanced the learning and memory of rat to find the method to improve the failure of memory which is the symptom of dementia.Method : In the experiment, rats were divided the control group (14 rat) which medicate the excipient into the sample group (17 rat) which medicates Hyangbujapalmutang. And the learning ability test and the memorv test was practiced to using the task of radial arm maze.The learning ability test had the presupposition that, when a rat which frequents 8 tracks makes am error not exceeding one time for 3 days without a break, it passes the test.First experiment compared total days when the control group passed the test with total days when the sample group it.The memory test practiced after 24 hours when the learning ability test was over. When a rat frequents 4 tracks, the gates is cut off during 30 seconds. Here the number of error at the control group with that of the sample group.Result: In the learning ability test, the sample group needed 5.82${\pm}$0.37 days to pass the test and the control group needed 6.43${\pm}$0.67 days. In the memory test, the sample group errored 0.29${\pm}$0.37 times and the control group errored 1.86${\pm}$0.78 times.Conclusion : In the learning ability test, the sample group passed the test earlier than the control group, but any statistical correlationship couldn't be found in it. In the memory test, the sample group had the pregnant reduction of the number of error in comparison with the control group.

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Improving Parallel Testing Efficiency of Memory Chips using NOC Interconnect (NOC 인터커넥트를 활용한 메모리 반도체 병렬 테스트 효율성 개선)

  • Hong, Chaneui;Ahn, Jin-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • 제68권2호
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    • pp.364-369
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    • 2019
  • Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

Self-adaptive testing to determine sample size for flash memory solutions

  • Byun, Chul-Hoon;Jeon, Chang-Kyun;Lee, Taek;In, Hoh Peter
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제8권6호
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    • pp.2139-2151
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    • 2014
  • Embedded system testing, especially long-term reliability testing, of flash memory solutions such as embedded multi-media card, secure digital card and solid-state drive involves strategic decision making related to test sample size to achieve high test coverage. The test sample size is the number of flash memory devices used in a test. Earlier, there were physical limitations on the testing period and the number of test devices that could be used. Hence, decisions regarding the sample size depended on the experience of human testers owing to the absence of well-defined standards. Moreover, a lack of understanding of the importance of the sample size resulted in field defects due to unexpected user scenarios. In worst cases, users finally detected these defects after several years. In this paper, we propose that a large number of potential field defects can be detected if an adequately large test sample size is used to target weak features during long-term reliability testing of flash memory solutions. In general, a larger test sample size yields better results. However, owing to the limited availability of physical resources, there is a limit on the test sample size that can be used. In this paper, we address this problem by proposing a self-adaptive reliability testing scheme to decide the sample size for effective long-term reliability testing.

Reallocation Data Reusing Technique for BISR of Embedded Memory Using Flash Memory (플래시 메모리를 이용한 내장 메모리 자가 복구의 재배치 데이타 사용 기술)

  • Shim, Eun-Sung;Chang, Hoon
    • Journal of KIISE:Computer Systems and Theory
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    • 제34권8호
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    • pp.377-384
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    • 2007
  • With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper, We proposed a reallocation algorithm for faulty memory part to efficient reallocation with row and column redundant memory. Reallocation information obtained from faulty memory by only every test. Time overhead problem occurs geting reallocation information as every test. To its avoid, one test resulted from reallocation information can save to flash memory. In this paper, reallocation information increases efficiency using flash memory.

Effect of Saenggitang on Learning and Memory Ability in Mice

  • Han Yun-Jeong;Chang Gyu-Tae;Kim Jang-Hyun
    • The Journal of Korean Medicine
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    • 제25권4호
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    • pp.51-60
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    • 2004
  • Objective : The effect Saenggitang (GT), which has been used for amnesia, in Oriental Medicine, on memory and learning ability, was investigated. Methods : Hot water extracts (HWE) of SGT were used for the studies. In passive avoidance performances (step through test), active avoidance performances (lever press test), Motor activity, pentobarbital-induced sleep, 20 and 50 mg/100g of SGT-HWE ameliorated the memory retrieval deficit induced by 40% ethanol. Results : The SGT-HWE did not affect the ambulatory activity of normal mice in normal condition. 20 and 50 mg/100g of SGT-HWE enhanced contextual fear memory, but not cued fear memory in a fear conditioning task, which requires the activation of the NMDA (N-methyl-D-aspartase) receptor. SGT-HWE did not affect the motor activity measured by the titling type ambulometer test performed immediately and 24 hr after the administration. SGT-HWE prolonged the sleeping time induced by 50 mg/kg pentobarbital in mice and decreased SMA (spontaneous motor activity) in active avoidance performances (lever press test). Conclusion : These results indicate that the SGT-HWE have an improving effect on the memory retrieval disability induced by ethanol and may act as a stimulating factor for activating the NMDA receptor. and the SGT-HWE has a tranquilizing and anti-anxiety action.

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The effect of Woohwangchungsimwon on the learning and memory in NOS inhibitor treated rats in Morris water maze. (우황청심원(牛黃淸心元)이 NOS inhibitor에 의한 흰쥐의 학습(學習) 및 기억장애(記憶障碍)에 미치는 영향(影響))

  • Baek Ji-Seong;Kim Jong-Woo
    • Journal of Oriental Neuropsychiatry
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    • 제10권2호
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    • pp.115-126
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    • 1999
  • This study was conducted to find out the effects of Woohwangchungsimwon on learning and memory in the NOS inhibitor treated rats. The Morris water maze was used in evaluating them. The result of the study was summarized as follows. 1. In the learning test, three groups have showed a gradual improvement of learning ability by repeating the trials in Morris water maze. WHCS group have showed statistical improvement than control group at 4,5,6 trial(p<0.05, p<0.01, p<0.01). 2. In the memory test, the first latency of WHCH group was statistically shortened than that of control group(p<0.05). 3. In the memory test, there was no statistical difference in the entry number between WHCH group and control. 4. In the memory test, there was no statistical difference in the memory score between WHCH group and control. The result of this experimental study presents that Woohwangchungsimwon has the improving effect on impaired learning and memory in NOS inhibitor treated rats, and implies that Woohwangchungsimwon may be one of the useful prescription for the treatment of vascular dementia after cerebral ischemia.

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Dynamic Testing for Word - Oriented Memories (워드지향 메모리에 대한 동적 테스팅)

  • Young Sung H.
    • Journal of the Korea Computer Industry Society
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    • 제6권2호
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    • pp.295-304
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    • 2005
  • This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.

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