• The KIPS Transactions:PartD
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• v.14D no.1 s.111
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• pp.21-34
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• 2007

According to recent rapid price drop and capacity growth of main memory, the number of applications on main memory databases is dramatically increasing. Cache miss, which means a phenomenon that the data required by CPU is not resident in cache and is accessed from main memory, is one of the major causes of performance degradation of main memory databases. Several cache-conscious trees have been proposed for reducing cache miss and making the most use of cache in main memory databases. Since each cache-conscious tree has its own unique features, more than one cache-conscious tree can be used in a single application depending on the application's requirement. Moreover, if there is no existing cache-conscious tree that satisfies the application's requirement, we should implement a new cache-conscious tree only for the application's sake. In this paper, we propose the cache-conscious generalized search tree (CC-GiST). The CC-GiST is an extension of the disk-based generalized search tree (GiST) [HNP95] to be tache-conscious, and provides the entire common features and algorithms in the existing cache-conscious trees including pointer compression and key compression techniques. For implementing a cache-conscious tree based on the CC-GiST proposed in this paper, one should implement only a few functions specific to the cache-conscious tree. We show how to implement the most representative cache-conscious trees such as the CSB+-tree, the pkB-tree, and the CR-tree based on the CC-GiST. The CC-GiST eliminates the troublesomeness caused by managing mire than one cache-conscious tree in an application, and provides a framework for efficiently implementing arbitrary cache-conscious trees with new features.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.193-204
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• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.349-354
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• 2009

In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.5
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• pp.590-597
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• 2002

Currently, with the increasing demand for combining cellular phone and PDA, various kinds of PDA-phones are being developed. A typical PDA-phone consists of a CDMA processor and a PDA processor. Generally, a UART serial communication port is used for inter-processor communication. However, the CDMA standard will need more data bandwidth over 2Mbps with the emergence of IMT-2000. The bandwidth requirement is beyond the capability of UART. In this paper, several inter-processor communication mechanisms are analyzed and especially Dual Port Memory and USB were chosen as the candidates for the new communication mechanism. A prototype PDA-phone board has been implemented for experiment. The experimental result shows that Dual Port Memory is better than USB in cost performance.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.17-22
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• 2010

As deployments of Flash memory are spreading out rapidly from tiny USB storages to large DB servers, interoperability become an indispensable requirement for Flash memory software architecture. For the purpose, many systems make use of the conventional FAT file system and FTL (Flash Translation Layer) software as a de facto standard. However, the tactless combination of the FAT file system and FTL does not satisfy diverse other requirements of a variety of systems. In this paper, we propose a novel reconfigurable integrated Flash memory software architecture, named INFLAWARE (INtegrated FLAsh softWARE) that supports not only interoperability but also reconfigurability and performance enhancement. Real implementation based experimental results have shown that INFLAWARE can achieve improvements of memory footprint up to 27% with an average of 19%, compared with the conventional FAT and FTL combination. Also, by using map_destroy technique, it can reduce response times of various applications up to 21% with an average of 10%.

• 한국전산유체공학회:학술대회논문집
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• 2007.10a
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• pp.194-199
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• 2007

IB (immersed boundary) method is one of the prominent tool in computational fluid dynamics for the analysis of flows over complex geometries. The IB technique simplyfies the solution procedure by eliminating the requirement of complex body fitted grids and it is also superior in terms of memory requirement. In this study we have developed numerical code (FOTRAN) for the analysis of 2D flow over a cylinder using IB technique. The code is validated by comparing the wake lengths and separation angles given by Guo et. al. We employed fractional-step procedure for solving the Navier-Stokes equations governing the flow and discrete forcing IB technique for imposing boundary conditions. Also we have developed a 3D code for the backward-facing-step flow and flow over a sphere. The reattachment length in backward-facing-step flow was compared with the one given by Nie and Armaly, which has proven the validity of our code.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1053-1056
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• 2004

Chunghwa Picture Tubes, LTD. (CPT) has developed a Novel TFT-LCD Driving Techniquel. This new technique is developed in combination with other state-of-the-art image processing solutions such as image compression / decompression, motion detection, and noise reduction. By applying the Novel Driving Technique to the high resolution TFT-LCD, it was found that the response time can be effectively reduced with a lower overall system cost by smaller frame memory requirement, lower EMI by less memory band-width. Likewise, higher display quality can also be achieved in that the unexpected noises generated by over-drive can be eliminated. The Novel TFT-LCD Driving Technique has been successfully implemented to the 30 inch WXGA (1280${\times}$768) resolution TFT LCD commercial TV module. It was found that the quality of moving picture was better improved compared with that of the conventional fast response driving method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.255-260
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• 1999

This paper shows the design of a high throughput 512-point FFT processor. The performance target of the 512-point FFT processor is to achieve data symbol rate required for OFDM systems. The memory requirement of the 512-point FFT processor is minimized by adopting shuffle memory system. The hardware cost of the 512-point in processor is further reduced by using a complex multiplier with a new strength reduction method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.187-190
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• 2005

There have been many studies to improve the performance of a database system focused on modifying data structure, data partitioning, and materializing strategy. The main contribution of this study is to propose a new alternative towards improving database performance by designing single table schema or processing queries virtually in main memory space. Material Requirement Planning(MRP) part explosion process has shown almost 2 times shorter under DB schema we suggested, and even more than 10 times shorter when separating and filtering policy of DB archiving process are assumed. Several experimental results are shown to illustrate the excellence of our solution.

• Journal of computational fluids engineering
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• v.9 no.3
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• pp.39-48
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• 2004

In the present study, an efficient implementation technique of the van Leer's implicit operator is suggested in accordance with the Roe's explicit operator. By using an efficient treatment of the off-diagonal terms, which occupy most of the memory requirement for the linear system of equations, it is shown that the improved scheme only requires less than 30% of memory and is approximately 10-20% faster than the baseline scheme.