• Journal of Digital Convergence
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• v.4 no.2
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• pp.143-151
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• 2006

The purpose of this paper is to make a design and implementation of a diagnosis system of learning misconception of students who learn 'be' verb in the English language by using fuzzy theory. In this system, a fuzzy cognitive map exposes the fact that students' perception and misunderstanding about 'the English' language have an intertwined relationship, and diagnoses causes of misconceptions of students by using fuzzy memory associative memory. It suggests that since most existing systems of rule based expert system have had several limitations, this system will be applied to diagnose learners' misconception of learning in varieties of education areas.

• 한국디지털정책학회:학술대회논문집
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• 2006.06a
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• pp.451-459
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• 2006

The purpose of this paper is to make a design and implementation of a diagnosis system of learning misconception of students who learn 'be' verb in the English language by using fuzzy theory. In this system, a fuzzy cognitive map exposes the fact that students' perception and misunderstanding about 'the English' language have an intertwined relationship, and diagnoses causes of misconceptions of students by using fuzzy memory associative memory. It suggests that since most existing systems of rule based expert system have had several limitations, this system will be applied to diagnose learners' misconception of learning in varieties of education areas.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.49-58
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• 2002

It takes 2 or 3 months to manufacture memory device. Defect has to exist owing to hundreds of processes. If there are too many defects, the memory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is needed for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The equipment development company had provided the redundancy analysis and each development company had developed and provided separately. So, to analyze the similar type of defects, redundancy analysis time can be very different by the manufacture. The purpose of this research is to strengthen the competitive price and to apply correlation concept in business for reducing the redundancy analysis time to repair the defects

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.664-665
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• 2013

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.11
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• The KIPS Transactions:PartD
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• v.9D no.4
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• pp.579-586
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• 2002

This paper propose an efficient algorithm for mining association rules in the large main memory systems. To do this, the paper attempts firstly to extend the conventional algorithms such as DHP and Partition in order to be compatible to the large main memory systems and proposes secondly an algorithm to improve Partition algorithm by applying the techniques of the hash table and the bit map. The proposed algorithm is compared to the extended DHP within the experimental environments and the results show up to 65% performance improvement in comparison to the expanded DHP.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.36-46
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• 2017

The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.2033-2036
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• 2004

A novel approach to estimate the real time moving trajectory of an object is proposed in this paper. The object position is obtained from the image data of a CCD camera, while a state estimator predicts the linear and angular velocities of the moving object. To overcome the uncertainties and noises residing in the input data, a Kalman filter and neural networks are utilized. Since the Kalman filter needs to approximate a non-linear system into a linear model to estimate the states, there always exist errors as well as uncertainties again. To resolve this problem, the neural networks are adopted in this approach, which have high adaptability with the memory of the input-output relationship. Kohonen Network(Self-Organized Map) is selected to learn the motion trajectory since it is spatially oriented. The superiority of the proposed algorithm is demonstrated through the real experiments.