• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.628-630
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• 2004

실시간 운영체제가 탑재되는 임베디드 시스템의 공간제약 특성상 한정된 자원을 가질 수밖에 없기 때문에 자원의 효율적인 사용 및 관리가 필수적이다. 특히 CPU 와 함께 한정된 크기의 메모리는 운영체제의 중요한 자원으로, 효율적인 메모리 관리를 통해 시스템의 성능을 향상시킬 수 있다. 본 논문에서는 실시간 운영체제의 동적 메모리 관리기법 중 메모리 풀에서의 메모리 누수 방지 기법을 설계 및 구현하였다

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.460-462
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• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.595-600
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• 2016

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between $109{\AA}$, $190{\AA}$, $387{\AA}$, and $818{\AA}$ which have the gate area $10^{-3}cm^2$. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1725-1732
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• 2024

In nuclear power plants, reactor coolant leakage can occur due to various reasons. Early detection of leaks is crucial for maintaining the safety of nuclear power plants. Currently, a detection system is being developed in Korea to identify reactor coolant system (RCS) leakage of less than 0.5 gpm. Typically, RCS leaks are detected by monitoring temperature, humidity, and radioactivity in the containment, and a water level in the sump. However, detecting small leaks proves challenging because the resulting changes in the containment humidity and temperature, and the sump water level are minimal. To address these issues and improve leak detection speed, it is necessary to quantify the leaks and develop an artificial intelligence-based leak detection system. In this study, we employed bidirectional long short-term memory, which are types of neural networks used in artificial intelligence, to predict the relative humidity in the leakage area for leak quantification. Additionally, an optimization technique was implemented to reduce learning time and enhance prediction performance. Through evaluation of the developed artificial intelligence model's prediction accuracy, we expect it to be valuable for future leak detection systems by accurately predicting the relative humidity in a leakage area.

• Steel and Composite Structures
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• v.19 no.3
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• pp.601-614
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• 2015

The Metal Magnetic Memory (MMM) method is a non-destructive testing method based on an analysis of the self-magnetic leakage field distribution on the surface of a component. It is used for determining the stress concentration zones or any irregularities on the surface or inside the components fabricated from ferrous-based materials. Thus, this paper presents the MMM signal behaviour due to the application of fatigue loading. A series of MMM data measurements were performed to obtain the magnetic leakage signal characteristics at the elastic, pre-crack and crack propagation regions that might be caused by residual stresses when cyclic loadings were applied onto the A283 Grade C steel specimens. It was found that the MMM method was able to detect the defects that occurred in the specimens. In addition, a justification of the Self Magnetic Flux Leakage patterns is discussed for demonstrating the effectiveness of this method in assessing the A283 Grade C steel under cyclic loadings.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1717-1723
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• 2007

In this study , quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) devices are fabricated using PLZT(10/30/70), PLT(10), PZT(30/70) thin film and their drain current properties are investigated. It is found that the drain current of quasi-MFISFET is directly influenced by the polarization strength of ferroelectric thin fan. Also, when the gate voltages are ${\pm}5\;and\;{\pm}10V$, the memory windows are 0.5 and 1.3V, respectively. It means that the memory window is changed with the variation of coercive voltage generated by the voltage applied on ferroelectric thin film. The electric field and the leakage current with time delay of PLZT(10/30/70) thin lam are measured to investigate the retention property of MFISFET device. Some material parameters such as current density constant, $J_{ETO}$, electric field dependent factor K and time dependent factor m are obtained. The variation of charge density with time is quantitatively analyzed by using the material parameters.