• The Journal of Society for e-Business Studies
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• v.14 no.4
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• pp.119-131
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• 2009

During a decade, e-Commerce environments supporting real-time transaction processing have been getting larger. In telecommunication and financial environments, research and building for main memory database systems have been doing to support real-time transaction processing. A research on indexing for fast transaction support focuses on reducing cache misses or reducing memory access latency when cache misses happen. In the paper, we propose a prefetch method for tree index structures to reduce memory access latency. We present a prefetch-efficient pCST-tree and show superiority of the proposed tree by experiments.

• Electronics and Telecommunications Trends
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• v.39 no.5
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• pp.98-107
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• 2024

Applications such as artificial intelligence continue to grow in complexity and scale. Thus, the demand for scalable computing is increasing for achieving faster data processing and improved efficiency. This requirement has led to the development of memory-centric computing and high-speed fabric interconnection technologies. Memory-centric computing reduces the latency and enhances the system performance by shifting the focus from the central processing unit to the memory, whereas high-speed fabric interconnects enable efficient data transfer across various computing resources. Technologies such as Gen-Z, OpenCAPI, and CCIX have been integrated into the CXL (Compute Express Link) standard since 2019 to improve communication and cache coherence. Ethernet-based interconnects such as RoCE, InfiniBand, and OmniXtend also play a crucial role in providing high-speed data transfer and low latency. We explore the latest trends and prospects of these technologies, highlighting their benefits and applications.

• Journal of IKEEE
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• v.25 no.3
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• pp.479-484
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• 2021

This paper proposed and designed a structure to achieve high performance with a small number of cores in GPGPU with SIMT structure. GPGPU for application to mobile devices requires a structure to increase performance compared to power consumption. In order to reduce power consumption, the number of cores decreased, but to improve performance, the size of the warp scheduler for managing threads was set to 4, which was greatly reduced than 32 of general GPGPU. Reducing warp size can reduce the number of idle cycles in pipelines and efficiently apply memory latency to reduce miss penalty when accessing cache memory. The designed GPGPU measured computational performance using a test program that includes floating point operations and measured power consumption through a 28nm CMOS process to obtain 104.5GFlops/Watt as a performance per power. The results of this paper showed about four times better performance per power compared to Tegra K1 of Nvidia

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.442-460
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• 2001

In video-on-demand(VOD) systems it is important to minimize initial latency and memory requirements. The minimization of initial latency enables the system to provide services with short response time, and the minimization of memory requirements enables the system to service more concurrent user requests with the same amount of memory. In VOD systems, since initial latency and memory requirement increase according to the increment of buffer size allocated to user requests, the buffer size allocated to user requests must be minimized. The existing static buffer allocation scheme, however, determines the buffer size based on the assumption that thy system is in fully loaded state. Thus, when the system is in partially loaded state, the scheme allocates user requests unnecessarily large buffers. This paper proposes a dynamics buffer allocation scheme that allocates user requests the minimum buffer size in fully loaded state as well as a partially loaded state. This scheme dynamically determines the buffer size based on the number of user requests in service and the number of user requests arriving while servicing current requests. In addition, through analyses and simulations, this paper validates that the dynamics buffer allocation outperforms the statics buffer allocation in initial latency and the number of concurrent user requests that can be supported. Our simulation results show that, in proportion to the static buffer allocation scheme, the dynamic buffer allocation scheme reduces the average initial latency by 29%~65%, and in a systems having several disks. increases the average number of concurrent user requests by 48%~68%. Our results show that the dynamic buffer allocation scheme significantly improves the performance and reduce the capacity requirements of VOD systems.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1209-1212
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• 2003

In this paper, we propose a SDRAM Controller. The SDRAM is often used a mainstream memory as embedded system memory due to its short latency, burst access and pipeline features. The proposed Controller provides essential functions for SDRAM initialization, read/write accesses, memory refresh and Burst access. Furthermore, the proposed controller is implemented in the form of SOFT IP. Therefore, it reduces the designer's effort greatly.

• Journal of Physiology & Pathology in Korean Medicine
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• v.16 no.5
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• pp.976-988
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• 2002

The aim of this study was to examine the memory and attention enhancement effect of YMG-1 and YMG-2, which are modified herbal extracts from Yukmijihwang-tang (YMJ). YMJ, composing six herbal medicine, has been used for restoring the normal functions of the body to consolidate the constitution, nourishing and invigorating the kidney functions for hundreds years in Asian countries. A series of studies reported that YMJ and its components enhance memory retention, protects neuronal cell from reactive oxygen attack and boost immune activities. Recently the microarray analysis suggested that YMG-1 protects neurodegeneration through modulating various neuron specific genes. A total of 55 subjects were divided into three groups according to the treatment of YMG-1 (n=20), YMG-2 (n=20) and control (C; n=15) groups. Before treatments, all of subjects were subjected to the assessments on neuropsychological tests of K-WAIS test, Rey-Kim memory test, and psychophysiological test of Event-Related Potential (ERP) during auditory oddball task and repeated word recognition task. They were repeatedly assessed with the same methods after drug treatment for 6 weeks. Although no significant effect of drug was found in Rey-Kim memory test, a significant interaction (P = .010, P < 0.05) between YMG-2 and C groups was identified in the scores digit span and block design, which are the subscales of K-WAIS. The very similar but marginal interaction (P = .064) between YMG-1 and C groups was found too. In ERP analysis, only YMG-1 group showed decreasing tendency of P300 latency during oddball task while the others tended to increase, and it caused significant interaction between session and group (p= .004). This result implies the enhancement of cognitive function in due to consideration of relationship between P300 latency and the speed of information processing. However, no evidence which could demonstrate the significant drug effect was found in neither amplitude or latency. These results come together suggest that YMG-1, 2 may enhance the attention, resulting in enhancement of memory processing. For elucidating detailed mechanism of YMG on learning and memory, the further studies are necessary.

• Journal of the Korean Society of Food Science and Nutrition
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• v.42 no.8
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• pp.1190-1196
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• 2013

The purpose of this study was to investigate the mechanism and effects of different types of ginseng on memory improvement in an experimental rat model. In this study, SD rats were induced for memory deficits through scopolamine treatment (1 mg/kg, i.p.) then administrated with ginseng extract for 7 weeks. The rats were divided into five groups: saline (1 mL/kg, NC: negative control), white ginseng (300 mg/kg, WG), red ginseng (300 mg/kg, RG), black ginseng (300 mg/kg, BG), and scopolamine (1 mg/kg, PC: positive control). The step through latency of the BG and RG groups was significantly longer than the PC group in the retention trial of multiple trial passive avoidance test. In the spatial reference memory triads of the Morris water maze test, the latency time of BG and RG was significantly lower than the PC group. In addition, in the prove test, the time spent in the platform quadrant of BG and RG groups were significantly longer than the PC group. Brain choline acetyltransferase (ChAT) activities BG and RG groups significantly increased compared to other groups. On the other hand, the levels of malondialdehyde (MDA) were significantly lower in the BG and RG groups compared to other groups. These result suggested that black ginseng could be useful to enhance learning memory and cognitive function by regulation of cholinergic enzymes.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.63-69
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• 2019

Recently, ultra-low latency flash storage devices such as Z-SSD and Optane SSD were introduced with the significant technological improvement in the storage devices which provide much faster response time than today's other NVMe SSDs. With such ultra-low latency, $10{\mu}s$, storage devices the cost of context switch could be an overhead during interrupt-driven I/O completion process. As an interrupt-driven I/O completion process could bring an interrupt handling overhead, polling or hybrid-polling for the I/O completion is known to perform better. In this paper, we analyze tail latency problem in a polling process caused by process scheduling in data center environment where multiple applications run simultaneously under one system and we introduce our adaptive polling selection technique which dynamically selects efficient processing method between two techniques according to the system's conditions.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.