• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.385-388
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• 2003

본 논문에서 제안하는 PFD(Phase Frequency Detector)는 Reset을 줄여 응답 속도의 특성을 향상시키기 위해 기존 회로인 Flip-Flop의 D-Latch circuit를 Memory Cell로 대신한 회로이다. 회로의 특성을 검증하기 위해 HSPICE Tool를 이용 simulation 하였으며 Hynix 0.35um CMOS 공정을 사용하였다.

• 한국통신학회논문지
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• 제25권4B호
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• pp.783-787
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• 2000

현재 사용되고 있는 개인용 컴퓨터의 중앙처리장치로서 주종을 이루고 있는 마이크로프로세서는 256KB, 혹은 512KB의 L2(Second Level) 캐쉬를 Direct Mapping, 32B 라인사이즈, 그리고 Write Allocation을 채택하지 않는 형태로 사용하고 있는데, 이러한 L2 캐쉬에서 Mapping 방식을 8-way Set Associative Mapping Procedure로 바꾸고, 라인사이즈를 늘려서 128B 이상으로 변경하고, 그리고 Write Allocation을 채택하였을 경우 그 적중률(Hit Ratio)이 약간의 하드웨어적 추가 비용만으로 2.5% 정도 개선됨을 확인하였다.

• 전자공학회논문지A
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• 제31A권6호
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• pp.177-187
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• 1994

In the design of modern computer systems, the speed gap between the CPUs and DRAMs has been a major concern. To relieve this problem at a low cost, several new DRAM architectures have been proposed. This study is aimed at evaluating quantitatively the impact of the new DRAM architectures (synchronous DRAM. dual-RAS synchronous DRAM, and enhanced DRAM) on the memory system performance. We developed a cache and memory simulator and performed various experiments using the traces generated from four benchmark programs. The simulation results show that the new DRAM architectures offer a better performance than a conventional one by 5~30% in a low cost system and their improvement in a high performance system is less than 1%. However, for resonable multiprogramming workoads, additional performance improvement of about 10~28% is expected in a high performance system while 1~3% in a low cost system.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.415-416
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• 2009

The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

• Smart Structures and Systems
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• 제14권5호
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• pp.765-784
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• 2014

In comparison with conventional shape memory actuated structures, antagonistic shape memory alloy (SMA) actuators permits a fully reversible two-way response and higher response frequency. However, excessive internal stress could adversely reduce the stroke of the actuators under repeated use. The two-way shape memory effect might further decrease the range of the recovered strain under actuation of an antagonistic SMA actuator unless additional components (e.g., spring and stopper) are added to regain the overall actuation capability. In this paper, the performance of all four possible types of SMA actuation schemes is investigated in detail with emphasis on five key properties: recovered strain, cyclic degradation, response frequency, self-sensing control accuracy, and controllable maximum output. The testing parameters are chosen based on the maximization of recovered strain. Three types of these actuators are antagonistic SMA actuators, which drive with two active SMA wires in two directions. The antagonistic SMA actuator with an additional pair of springs exhibits wider displacement range, more stable performance under reuse, and faster response, although accurate control cannot be maintained under force interference. With two additional stoppers to prevent the over stretch of the spring, the results showed that the proposed structure could achieve significant improvement on all five properties. It can be concluded that, the last type actuator scheme with additional spring and stopper provide much better applicability than the other three in most conditions. The results of the performance analysis of all four SMA actuators could provide a solid basis for the practical design of SMA actuators.

• 한국컴퓨터산업학회논문지
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• 제2권2호
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• pp.211-218
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• 2001

본 논문에서는 동영상 부호화기에서 프레임 메모리 인터페이스의 하드웨어 구현을 위해 기존의 DRAM이 아닌 SDRAM을 사용하여 효율적인 메모리 맵의 구조를 제안한다. 동일한 버스에서도 효과적인 메모리 맵과 내부 버퍼 크기를 줄여 하드웨어 복잡도을 개선하고 내부 로직을 간략화하여 면적을 최소화하였다. 기존의 시스템은 매크로 블록 단위로 메모리에 저장하고 다시 출력을 위해서 랜덤하게 저장되어 있는 데이터를 액세스하여 많은 시간을 소비한다. 따라서 데이터를 라인 단위로 저장 및 처리하므로 메모리의 엑세스 시간을 효과적으로 줄일 수 있는 방법을 제시하였다.

• Journal of Korean Neurosurgical Society
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• 제52권1호
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• pp.21-26
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• 2012

Objective : To evaluate a new posterior atlantoaxial fixation technique using a nitinol shape memory loop as a simple method that avoids the risk of vertebral artery or nerve injury. Methods : We retrospectively evaluated 14 patients with atlantoaxial instability who had undergone posterior C1-2 fusion using a nitinol shape memory loop. The success of fusion was determined clinically and radiologically. We reviewed patients' neurologic outcomes, neck disability index (NDI), solid bone fusion on cervical spine films, changes in posterior atlantodental interval (PADI), and surgical complications. Results : Solid bone fusion was documented radiologically in all cases, and PADI increased after surgery (p<0.05). All patients remained neurologically intact and showed improvement in NDI score (p<0.05). There were no surgical complications such as neural tissue or vertebral artery injury or instrument failure in the follow-up period. Conclusion : Posterior C1-2 fixation with a nitinol shape memory loop is a simple, less technically demanding method compared to the conventional technique and may avoid the instrument-related complications of posterior C1-2 screw and rod fixation. We introduce this technique as one of the treatment options for atlantoaxial instability.

• 한국정보과학회논문지:시스템및이론
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• 제30권7_8호
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• pp.331-340
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• 2003

가격대비 성능이 좋은 저가의 상업용 SMP가 클러스터 시스템의 노드로 많이 사용되고 있다. 본 논문에서는 이러한 SMP 클러스터 상에서 KDSM을 확장해 소프트웨어 분산공유메모리를 구현하고 성능을 평가하였다. 본 논문의 SDSM 시스템은 HLRC 메모리 모델을 제공한다. 또한 같은 SMP 노드내에서 실행되는 프로세스 간에는 메모리 공유를 통해 페이지 획득 및 메시지 전달을 줄여 성능을 향상시켰다. 100Mbps Fast Ethernet으로 연결된 8노드의 2-way 펜티엄-III SMP 클러스터 상에서 구현되었고 통신계층은 TCP/IP를 사용한다. 8개의 응용프로그램을 실행시켜 얻은 성능 평가에서는 기존의 단일프로세스 프로토콜과 비교해 최대 33%의 성능 향상과 13%-52%의 페이지 획득 감소가 나타났다.

• 대한한의학회지
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• 제39권4호
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• pp.1-15
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• 2018

Objectives: Cerebral ischemia results from a variety of causes that cerebral blood flow is reduced due to a transient or permanent occlusion of cerebral arteries. Reactive astrocytes and microglial activation plays an important role in the neuronal cell death during ischemic insult. Acupunctural treatment is effective for symptom improvement in cerebrovascular accident, including cerebral ischemia. Methods: In the present study, the effects of acupuncture at the ST40 acupoint on short-term memory and apoptosis in the hippocampal CA1 region following transient global cerebral ischemia were investigated using gerbils. Transient global ischemia was induced by occlusion of both common carotid arteries with aneurysm clips for 5 min. Acupuncture stimulation was conducted once daily for 7 consecutive days, starting one day after surgery. Results: In the present results, ischemia induction deteriorated short term memory, increased apoptosis, and induced reactive astrocyte and microglial activation. Acupuncture at ST40 acupoint ameliorated ischemia-induced short-term memory impairment by suppressing apoptosis in the hippocampus through down-regulation of reactive astrocytes and microglial activation. Conclusion: The present study suggests that acupuncture at the ST40 acupoint can be used for treatment of patients with cerebral stroke.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 1996년도 추계연구발표회 논문개요집
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• pp.28-29
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• 1996