• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.821-830
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• 2006

As internet worms are spread out worldwide, the detection and filtering of worms becomes one of hot issues in the internet security. As one of implementation methods to detect worms, the Linux Netfilter kernel module can be used. Its basic operation for worm detection is a string matching where coming packet(s) on the network is/are compared with predefined worm signatures(patterns). A worm can appear in a packet or in two (or more) succeeding packets where some part of worm is in the first packet and its remaining part is in its succeeding packet(s). Assuming that the maximum length of a worm pattern is less than 1024 bytes, we need to perform a string matching up to two succeeding packets of 2048 bytes. To do so, Linux Netfilter keeps the previous packet in buffer and performs matching with a combined 2048 byte string of the buffered packet and current packet. As the number of concurrent connections to be handled in the worm detection system increases, the total size of buffer (memory) increases and string matching speed becomes low In this paper, to reduce the memory buffer size and get higher speed of string matching, we propose a string matching scheme without using buffer. The proposed scheme keeps the partial matching result of the previous packet with signatures and has no buffering for previous packet. The partial matching information is used to detect a worm in the two succeeding packets. We implemented the proposed scheme by modifying the Linux Netfilter. Then we compared the modified Linux Netfilter module with the original Linux Netfilter module. Experimental results show that the proposed scheme has 25% lower memory usage and 54% higher speed compared to the original scheme.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.283-286
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• 2000

One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).

• Proceedings of the Materials Research Society of Korea Conference
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• 2006.05a
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• pp.21.1-21.1
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• 2006

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.20-25
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• 2016

This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.186-189
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• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• Journal of the Korean Ceramic Society
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• v.42 no.2 s.273
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• pp.104-109
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• 2005

To study the role of PbO as the buffer layer, Pt/PZT/PbO/Si with the MFIS structure was deposited on the p-type (100) Si substrate by the r.f. magnetron sputtering with $Pb_{1.1}Zr_{0.53}Ti_{0.47}O_3$ and PbO targets. When PbO buffer layer was inserted between the PZT thin film and the Si substrate, the crystallization of the PZT thin films was considerably improved and the processing temperature was lowered. From the result of an X-ray Photoelectron Spectroscopy (XPS) depth profile result, we could confirm that the substrate temperature for the layer of PbO affects the chemical states of the interface between the PbO buffer layer and the Si substrate, which results in the inter-diffusion of Pb. The MFIS with the PbO buffer layer show the improved electric properties including the high memory window and low leakage current density. In particular, the maximum value of the memory window is 2.0V under the applied voltage of 9V for the Pt/PZT(200 nm, $400^{\circ}C)/PbO(80 nm)/Si$ structures with the PbO buffer layer deposited at the substrate temperature of $300^{\circ}C$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.4
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• pp.268-279
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• 1986

Recently, the improtance of the ISDN has been emphasized for the new services in the future information society. In this paper, new application of statistical multiplexer which can be used for CCITT D-channel multiplexing is suggested. The basic architecture of statistical multiplexer which can interleave eleven 16Kbps D-channels into one 64Kbps B-channel is also proposed. The necessary buffer size was estimated by computer simulation considering data traffic intensity, signal arrival length distribution and buffer overflow probability. Based on this buffer size, the basic architecture of the statistical multiplexer has been survetyed and hardware design principles are also studied.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.360-363
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• 2003

In this paper, we investigated SiNx film as a buffer layer of TFT-FRAM. Buffer layers were prepared by two step process of a $N_2$ plasma treatment and subsequent $SiN_x$ deposition. By employing $N_2$ plasma treatment, interface traps such as mobile charges and injected charges were removed, hysteresis of current-voltage curve disappeared. After $N_2$ plasma treatment, a leakage current was decreased about 2 orders. From these results, it is possible to perform the plasma treating process to make a good quality buffer layer of MFIS-FET or capacitor as an application of non-volatile memory.