• The Transactions of the Korea Information Processing Society
• /
• v.5 no.9
• /
• pp.2395-2403
• /
• 1998

Memory allocation problem has two independent goals: minimization of number of memories and minimization of number of registers in one memory Our concern is the ordering of the bindings during memory allocation. We formulate and analyze three different memory allocation algorithms b) changing their binding order. It is shown that when we combine these subtasks and solve them simultaneously by heuristic cost function significant savings (up to 20%) can be obtained in the total area of memories.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1991.10a
• /
• pp.1-4
• /
• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2011.05a
• /
• pp.244.1-244.1
• /
• 2011

Memristors have been studied for many years due to better scalability than DRAMs and FLASH memories thus they are considered now as a strong candidate for future memories. To describe the electrical behavior of memristors, various memristor models have been developed. Especially, many kinds of window function have been used to express the non-linearity of memristors which are thought to cause different voltage-current relationships in memristors. In this paper, the previous memristor models with different window functions are compared and analyzed. This comparative study can be very useful in not only understanding the diversity in memristor's electrical behaviors but also developing memristor circuits. This work was financially supported by the SRC/ERC program of MOST/KOSEF (R11-2005-048-00000-0). The CAD tools were supported by the IC Design Education Center (IDEC), Korea.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.852-856
• /
• 2005

This paper proposes a new design of the ECG simulator with high resolution by using small amount of memories based on discrete least square estimation equations instead of reading the stored data inside the look-up table. The experimental results have shown that the ECG simulator using discrete least square estimation equations can display the bipolar limb leads ECG signals with low PRD (percent root-mean-square difference) while taking the less amount of memories than the previous method which used the look-up table to store ECG data for ECG simulation.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.5
• /
• pp.699-708
• /
• 1990

This paper proposes two test procedures for detecting functional faults in semiconductor random access memories (RAM's) and a new testimg scheme to execute the proposed test procedures. The first test procedure detects stuck-at faults, coupling faults and decoder faults, and requires 19N operations, which is an improvement over conventional procedures. The second detects restricted patternsensitive faults and requires 69N operations. The proposed scheme uses Built-In Self Testing (BIST) techniques. The scheme can write into more memory cells than I/O pins can in a write cycle in test mode. By using the scheme, the number of write operations is reduced and then much testing time is saved.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.8
• /
• pp.1201-1210
• /
• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.1 no.1
• /
• pp.35-43
• /
• 2001

In this paper, we propose a design method for GBSB (generalized brain-state-in-a-box) based associative memories. Based on the theoretical investigation about the properties of GBSB, we parameterize the solution space utilizing the limited number of parameters sufficient to represent the solution space and appropriate to be searched. Next we formulate the problem of finding a GBSB that can store the given pattern as stable states in the form of constrained optimization problems. Finally, we transform the constrained optimization problem into a SDP(semidefinite program), which can be solved by recently developed interior point methods. The applicability of the proposed method is illustrated via design examples.

• Journal of Power System Engineering
• /
• v.3 no.2
• /
• pp.79-83
• /
• 1999

We implemented a system that can change laser beam directions rapidly by controlling the galvano-mirror, on which a mirror is mounted, with a computer. We show that a laser projection can be realized by programming our system properly, and that it can also be used for multiplexing 2-dimensional image information in the data storage of holographic memories efficiently.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.7
• /
• pp.117-124
• /
• 1994

In this pape, we propose a graph-theoretic approach for solving the allocation problem for the synthesis of datapaths based on multiport memories. An efficient algorithm is devised by using the weighted bipartite matching algorithm to assign variables to each port of memory modules. The proposed algorithm assigns program variables into a minimum number of multiport memory modules such that usage of memory elements and interconnection cost can be kept minimal. Experimental results show that the proposed algorithm generates the datapaths with fewer registers in memory modules and less interconnection cost for several benchmarks available from the literatures.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.235-238
• /
• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.