• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.515-522
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• 2009

In this paper, a novel transmission scheme with spatial modulation is proposed for coded orthogonal frequency division multiplexing (OFDM). The multiple-input multiple-output (MIMO) technique, so-called spatial modulation (SM), divides input data into antenna index and data signals, transmitting data signals through the specific antenna chosen by the antenna index. In order to retrieve data stream at the receiver, SM needs to detect the antenna index which means that data signals are transmitted via a certain antenna. For this reason, it should be guaranteed that channel matrix is orthogonal. For the real environment, a MIMO channel has difficulty in maintaining orthogonality due to spatial correlation. Moreover, the receiver of the conventional SM is operated by hard decision, so that this scheme has a limit to be adopted for practical systems. Therefore, soft-output demappers for the conventional and proposed schemes are derived to detect antenna index and data stream by soft decision, and a novel transmission scheme combined with spatial modulation is proposed to improve the bit error rate (BER) performance of the conventional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.1
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• pp.109-117
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• 2013

Polar codes are the first provable error correcting code achieving the symmetric channel capacity in a wide case of binary input discrete memoryless channel(BI-DMC). However, finite length polar codes have an error floor problem with successive-cancellation list(SCL) decoder. From previous works, we can solve this problem by concatenating CRC(Cyclic Redundancy Check) codes. In this paper we propose to make polar codes having extended-minimum distance from original polar codes without outer codes using correlation with generate matrix of polar codes and that of RM(Reed-Muller) codes. And we compare performance of proposed polar codes with that of polar codes concatenating CRC codes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.5
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• pp.11-20
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• 2002

Based on regularization principles, we propose a new dequantization scheme on DCT-based transform coding for reducing of blocking artifacts and minimizing the quantization error. The conventional image dequantization is simply to multiply the received quantized DCT coefficients by the quantization matrix. Therefore, for each DCT coefficients, we premise that the quantization noise is as large as half quantizer step size (in DCT domain). Our approach is based on basic constraint that quantization error is bounded to ${\pm}$(quantizer spacing/2) and at least there are not high frequency components corresponding to discontinuities across block boundaries of the images. Through regularization, our proposed dequantization scheme, sharply reduces blocking artifacts in decoded images. Our proposed algorithm guarantees that the dequantization process will map the quantized DCT coefficients will be evaluated against the standard JPEG, MPEG-1 and H.263 (with Annex J deblocking filter) decoding process. The experimental results will show visual improvements as well as numerical improvements in terms of the peak-signal-to-noise ratio (PSNR) and the blockiness measure (BM) to be defined.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.