• 한국재료학회:학술대회논문집
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• 한국재료학회 1993년도 춘계학술발표회
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• pp.43-44
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• 1993

In this study SOI MOSFET model of the structure with 4-terminals and 3-interfaces is proposed. An SOI MOSFET is modeled with the equivalent circuit considered the interface capacitances. Parameters of SOI MOSFET device are extracted, and the electrical characteristics due to back-bias change is simulated. In SOI-MOSFET model device we describe the characteristics of threshold voltage, subthreshold slope, maxium electrical field and drain currents in the front channel when the back channel condition move into accmulation, depletion, and inversion regions respectively.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 추계학술대회 논문집
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• pp.218-220
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• 2008

This paper describes buck converter's MOSFET driver for high-brightness LED strings. The power driving high-side MOSFET is supplied from the power source of control circuit part. The practical considerations and future work are also described.

• 대한전자공학회논문지
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• 제13권1호
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• pp.11-15
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• 1976

게이트 전류가 흐르지 않는 MOSFET를 사용한 단안정 멀티바치브레이터는 도전시에도 게이트 전압이 일정하게 유지되지 않기 때문에 이 전압을 기준으로 한 회로해석이나 설계는 매우 어려워서, 비교적 간단히 해결할 수있는 도식방법을 소개하였다. 즉 각FET의 전압이득곡선을 구하고 이 유선의 기본적인 성질과 국로 설계에 이용하는 방법들에 대해서 논하였다. In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

• Journal of Power Electronics
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• 제17권2호
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• pp.561-569
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• 2017

Power converter design requires simulation accuracy. In addition to the requirement of accurate models of power semiconductor devices, this paper highlights the role of considering a very good description of the converter circuit layout for an accurate simulation of its electrical behavior. This paper considers a simple experimental circuit including one switching cell where a MOSFET transistor controls the diode under test. The turn-off transients of the diode are captured, over which the circuit wiring has a major influence. This paper investigates the necessity for accurate modeling of the experimental test circuit wiring and the MOSFET transistor. It shows that a simple wiring inductance as the circuit wiring representation is insufficient. An adequate model and identification of the model parameters are then discussed. Results are validated through experimental and simulation results.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2002년도 추계학술대회논문집
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• pp.204-209
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• 2002

A PDP(Plasma Display Panel) module consists of a discharge panel, a SMPS(Switched Mode Power Supply) for power supply, driving boards for panel control, and a logic board. Driving boards supply high voltage pulses to induce glow discharge in the PDP panel. The electrical pulses excite the circuit elements and subsequently generate acoustic noises. The main sources of the noise in the circuit are the transformer of SMPS and the power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) of driving boards, and the heat sinks often amplify the noise level. The reduction of the acoustic noises was achieved by modifying both the structural and circuit elements. The structural method was executed by the improvement of heat sinks. The optimization of SMPS and condensers was carried out for the circuit elements.

• 한국정보통신학회논문지
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• 제11권10호
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• pp.1910-1915
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• 2007

본 논문에서는 NQS(non-quasi-static)효과를 고려한 FD(fully depleted)-SOI(silicon-on-insulator) MOSFETs의 고주파 소신호 모델링을 위한 등가회로 변수들을 간단하고 정확히 추출하는 방법을 제시하였다. 제시된 추출방법은 임피던스와 어드미턴스 행렬계산으로 S-파라미터의 측정 결과로부터 MOSFET의 외부 기생용량과 기생저항을 제거하여 물리적인 특성을 바탕으로 한 MOSFET의 내부등가회로변수가 간단히 추출되어진다. 제시된 방법으로 등가 회로를 구한 후 Y-파라미터를 계산하여 측정치와 비교한 결과 500MHz부터 200Hz까지 잘 일치함을 확인하였다.

• 반도체디스플레이기술학회지
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• 제21권2호
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• pp.101-106
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• 2022

In this paper, WBG semiconductor such as SiC and GaN were applied as power switches for LCL circuit that can be applied to satellite power systems and the test results of the LCL circuit are reported. P-channel MOSFET and N-channel MOSFET, which were generally used in the conventional LCL circuit, were applied together to expand the utility of the test results. The design and stability evaluation were performed using a Micro Cap circuit simulation program. For the test circuit, a module using each switch was manufactured, and a total of 5 modules were manufactured and the steady state and transient state characteristics were compared. From the experimental results, the LCL circuit for power supply of the satellite power system constructed in this paper satisfied the constant current and constant voltage conditions under various operating conditions. The P-channel MOSFET showed the lowest efficiency characteristics, and the three N-channel switches of Si, SiC and GaN showed relatively high efficiency characteristics of up to 99.05% or more. In conclusion, it was verified that the on-resistor of the switch had a direct effect on the efficiency and loss characteristics.

• 한국전기전자재료학회논문지
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• 제25권5호
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• pp.340-344
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• 2012

Protected Circuit Module protects battery from over-charge and over-discharge, also prevents accidental explosion. Therefore, power MOSFET is essential to operate as a switch within the module. To reduce power loss of MOSFET, the on state voltage drop should be lowered and the switching time should be shorted. However there is trade-off between the breakdown voltage and the on state voltage drop. The TDMOS can reduce the on state voltage drop. In this paper, effect of design parameter variation on electrical properties of TDMOS, were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get 65% higher breakdown voltage and 17.4% on resistance enhancement.

• 한국전자통신학회논문지
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• 제6권1호
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• pp.118-122
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• 2011

플래시메모리의 쓰기나 소거 등의 프로그래밍 동작을 위해서는 각기 다른 고전압이 필요하며, 이를 위해서 차지펌프회로가 사용되어 왔다. 본 논문에서 제안되는 차지펌프회로는 VCO를 이용하여 외부에서 인가되는 기준전압과 차지펌프의 출력이 일치하도록 클락 주파수를 조절해줌으로서 공정에 의한 오차뿐만 아니라 차지펌프의 각 단을 구성하는 MOSFET의 바디효과에 관계없이 예측 가능한 출력을 발생하는 회로이다.

• 한국인터넷방송통신학회논문지
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• 제10권6호
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• pp.243-249
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• 2010

본 논문에서는 대칭형 이중 게이트 MOSFET의 회로해석에 대한 등가모델을 제시하고자 해석적 모델을 연구하였다. 본 연구의 해석적 모델에 사용된 방법은 2차원 포아송 방정식의 해를 가정하여 표면 전위 관계식을 유도하여 실리콘 몸체 내의 전위분포를 풀어 드레인 전압 변화에 대한 문턱전압 관계식을 도출하였다. 단채널 및 장채널 실리콘 채널에서 모두 해석이 가능한 해석적 모델을 적용 가능하도록 하기 위해 MOSFET의 채널 길이에 따른 제한된 지수함수를 적용함으로써 수백 나노미터까지 해석이 가능한 대칭형 이중 게이트 MOSFET 해석적 모델을 연구하였다.