• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.8-11
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• 1997

This study makes SrTiO$_{3}$ with nonpolarity among ferroelectrics by RF sputtering as dielectric layer, produces thin film of Si/SrTiO$_{3}$ and Si/Ti/SrTiO$_{3}$ of MOS structure using Ti as buffer layer, measures and examines the electrical features with optical refractive index, absorption rate, permittivity, photon energy and as a result, ferroelectrics oscillation occurrs by the interaction within a film by light temperature and the absorption of thin film with Ti as buffer layer is increased. It is found that the pea\ulcorner of permittivity value of Ti/SrTiO$_{3}$ thin film has low values and is appeared late and as dipole which is found in dielectric is shown, the experiment satisfies the theory In the nature of permittivity by photon energy, imaginary value is higher and current variation slope of thin film of thickness SrTiO$_{3}$ has lower values in reverse bias.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1286-1293
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• 1988

A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.90-93
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• 1992

In this paper, MOS characteristics of gate dielectrics prepared by furnace oxidation of Si in an $N_2O$ ambient have been studied. Compared with the oxides grown in $O_2$, $N_2O$ oxides show significantly improved breakdown field and low flat band voltage. Also, $N_2O$ oxide is more controllable for ultrathin film growth than $O_2$ oxide. This improvement is caused by nitrogen incorporation into the $N_2O$ oxide. Therefore, the nitrogen-rich-layer at the Si/$SiO_2$ interface formed during $N_2O$ oxidation not only strengthen $N_2O$ oxide structure at the interface and improves the gate dielectric quality, it also acts as a oxidant diffusion barrier that reduces the oxidation rate significantly.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.642-645
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• 2012

MANET has disadvantage for information intrusion caused from non-infra structure. That is based on mixed problems caused from terminal devices has no capability of various resources using abilities to run intrusion prevention function, and also from difficulty of no easy using infra structural server like as firewall. In this paper, transmission performances, be effected from information intrusion and IDS(Intrusion Detection System), are analyzed for large scale MANET, and weakness from information intrusion of MANET are studied. This study is for large scale MANET which has some large communication area and lots of nodes, voice traffic, based on VoIP protocols, is considered as application services be transmitted over MANETs. Computer simulation using NS-2 is used to measure and show MOS and call connection ratios.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.41-46
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• 2002

In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.941-943
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• 1999

In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.503-504
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• 2006

This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.