• 전기학회논문지
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• 제58권12호
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• pp.2420-2424
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• 2009

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $Al_2O_3/p-Si$ structures. The $Al_2O_3$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. Trimethylaluminum [$Al(CH_3)_3$, TMA] and $H_2O$ were used as the aluminum and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TMA pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $Al_2O_3$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• 한국전기전자재료학회논문지
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• 제25권1호
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• pp.33-36
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• 2012

In this study, the thickness effects of $Al_2O_3$ layer on the sensing properties of $SiO_2/Al_2O_3$ (OA) stacked membrane were investigated using electrolyte-insulator-semiconductor (EIS) structure for high quality pH sensor. The $Al_2O_3$ layers with a respective thickness of 5 nm, 15 nm, 23 nm, 50 nm, and 100 nm were deposited on the 5-nm-thick $SiO_2$ layers. The electrical characteristics and sensing properties of each OA membranes were investigated using metal-insulator-semiconductor (MIS) and EIS devices, respectively. As a result, the OA stacked membrane with 23-nm-thick $Al_2O_3$ layer shows the excellent characteristics as a sensing membrane of EIS sensor, which can enhance the signal to noise ratio.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.813-815
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• 1992

Accurate Capacitance-Voltage characteristics of Metal-Insulator-Semiconductor (MIS) devices in narrow band-gap semiconductors are presented. The unique band structure of narrow band-gap semiconductors is taken into account such as non-parabolicity and degeneracy. Compensated and partially ionized impurities either in the bulk or the space charge region are also considered. HgCdTe is a defect semiconductor, so this approach is very important for characterization and analysis of MIS devices.

• 한국전기전자재료학회논문지
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• 제13권5호
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• pp.365-370
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• 2000

Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.93-94
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• 2006

나노급 CMOS 기술에서 high-k 물질을 이용하여 게이트 유전막을 형성하고자 하는 연구가 활발히 진행되고 있다. 본 논문에서는 high-k 물질인 $TiO_2$의 특성에 대한 연구를 수행하였다. $TiO_2$를 APCVD법으로 p-type 실리콘 기판에 $50{\AA}{\sim}300{\AA}$ 두께로 증착하였고, evaporator를 이용하여 $TiO_2$ 박막위에 Al을 증착하여 MIS소자를 제작하였다. 두께를 가변 하여 Capacitance-Voltage (C-V) 특성을 측정, 분석하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.84-87
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• 2003

Carbon nitride ($CN_x$) films were prepared by reactive RF magnetron sputtering system with DC bias at various deposition conditions and the electrical properties were investigated. The films were characterized by fourier transform infrared (FTIR) spectroscopy, and X-ray photoelectron spectroscopy (XPS). The metal-insulator-semiconductor (MIS) capacitor which has $Al/CN_x/Si$ structure was designed and fabricated to investigate the capacitance-voltage (C-V) characteristics. Dielectric constant of carbon nitride films is very small.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 영호남 합동 학술대회 및 춘계학술대회 논문집 센서 박막 기술교육
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• pp.152-155
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• 2006

Carbon nitride ($CN_X$) films were prepared by reactive RF magnetron sputtering system at various deposition conditions and the C-V characteristics of MIS(metal - insulator - semiconductor) capacitors that have the structures of Al/$CN_x$/p-Si/Al and Al/$CN_x$/$Si_3N_4$/p-Si/Al were investigated. The resistivity of carbon nitride was above $2.40{\times}10^8{\Omega}{\cdot}cm$ at room temperature. The C-V plot showed a typical capacitance-voltage characteristics of semiconductor insulating layers, while it showed hysterisis due to interface charges. Amorphous carbon nitride (a-$CN_x$) films, that have relatively high resistivity and low dielectric constant could be useful as interlayer insulator materials of VLSI(very large-scale integration) and ULSI(ultra large-scale integration).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.342-342
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• 2011

산화막은 반도체 공정 중 가장 핵심적이며 기본적인 물질이다. 반도체 소자에서 내부의 캐리어들의 이동을 막고 전기를 절연시켜주는 절연체로서 역할을 하게 된다. 실제로 제작된 산화막에서는 dangling bond 혹은 내부에 축적되는 charge들의 의해 leakage가 생기게 되고 그에 따라 산화막의 특성은 저하되게 된다. 내부에서 특성을 저하시키는 defect을 감소시키기 위해 Plasma Treatment에 따른 특성변화를 관찰하였다. 본 연구에서는 최적화 시킨 Flexible TFT제작을 위해 저온에서 Silicon Oxide로 형성한 Gate Insulator에 각각 N2O, H2, NH3가스를 주입 후 Plasma처리를 하였다. 특성화 시킨 Gate Insulator를 이용하여 MIS(Metal-Insulator-Semiconductor)구조를 제작 후 C-V curve특성변화, Dit의 감소, Stress bias에 따른 stability를 확인 하였다.

• 한국결정성장학회지
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• 제14권3호
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• pp.90-94
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• 2004

The variation of electrical properties of (Ba,Sr)$TiO_3$ [BST] thin films for Metal-Insulator-Semiconductor (MIS) capacitors was investigated. BST thin films were deposited on p-Si(100) substrates by the RF magnetron sputtering with temperature range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of AUBST/$SiO_2$/Si sandwich structure were measured for various conditions. We examined the characteristics of MIS capacitor with various oxygen pressure, substrate temperature and (Ba+Sr)/Ti ratio. It was found that the leakage current was reduced in MIS capacitor with high quality $SiO_2$ layer was grown on bare p-Si substrate by thermal oxidation. The BST MIS structure showed relatively high capacitance even though it is the combination of high-dielectric BST thin films and $SiO_2$ layer. The charge state densities of the MIS capacitors and Current-voltage characteristics of the MIS capacitor were investigated. By applying $SiO_2$ layer between BST thin films and Si substrate, low leakage current of $10^{-10}$ order was observed.