• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.89-92
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• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.

• The KIPS Transactions:PartB
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• v.16B no.2
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• pp.151-156
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• 2009

This paper proposes a Gaussian mixture model(GMM)-based music discrimination system for FM broadcasting. The objective of the system is automatically archiving music signals from audio broadcasting programs that are normally mixed with human voices, music songs, commercial musics, and other sounds. To improve the system performance, make it more robust and to accurately cut the starting/ending-point of the recording, we also added a post-processing module. Experimental results on various input signals of FM radio programs under PC environments show excellent performance of the proposed system. The fixed-point simulation shows the same results under 3MIPS computational power.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.85-96
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• 2008

One of the typical methods to prevent tampering and reverse engineering on executable codes is to encrypt them. This paper proposes a code block cipher method based on key chaining to encrypt the code. The block cipher by key chaining has been known to be inadequate for encrypting the code with control transfer, even though the key chaining has advantage of hiding the keys in blocks and making the individual keys different from block to block. This paper proposes a block transformation and duplication method to apply the block cipher by key chaining to the executable codes with control transfer instructions, and shows the idea works with the MIPS instruction set.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.825-827
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• 1997

This paper presents a robot which is steered by vision system. The proposed robot system has an AM188ES CPU(5.3 MIPS) and 2DC motors with encoder and turns accurately at any speed and shows a movement like a human controlled car using a steering wheel. To the robot only steering angle value is sent without considering the speed. We present how to control this robot using our real time vision system.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.257-260
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• 2001

본 논문에서는 2 채널 MAIN 프로필 MPEG-2 AAC 복호화 시스템의 구조를 제안하고 구현하였다. 복호화 알고리듬의 구조적인 모듈화에 근거하여, 시스템 설계 과정에서 전체 시스템을 3 개의 하드웨어 모듈로 분할하였다. 전체 시스템은 허프만 복호화기, 예측기, 20 비트 고정소수점 DSP 코어로 이루어져 있다. 허프만 복호화기는 주어진 작업을 1 클럭 사이클 내에 수행할 수 있는 고속의 하드와이어드 모듈이고, 예측기는 높은 해상도를 가지고 다른 모듈들과 병렬처리가 가능한 구조를 가진 모듈이다. 구현된 시스템은 16.9 MIPS 로 2 채널의 MPEG-2 AAC 비트열을 고음질로 복호화할 수 있다.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.249-252
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• 2004

본 논문에서는 TeakLite DSP 프로세서를 이용하여 캠코더에서 레코딩을 할 때 모터 소음과 주변 잡음이 입력되어 오디오 신호의 명료도가 떨어지는 문제점을 해결하기 위한 잡음 제거 기법의 실시간 구현에 대해서 기술하고자 한다. 잡음 제거를 위해서는 일반적으로 많이 사용되고 있는 Spectral Subtraction 기법을 사용하였다. 알고리즘 구현시 MIPS 감소에 효과적이었던 최적화 기법들을 적용하여 TeakLite DSP 프로세서에서 최적화되어 동작하도록 하였다. 최적화된 Spectral Subtraction 어셈블리 코드는 TeakLite DSP 프로세서에서 32 kHz, 16 bit 입력에 대해 40 MIPS에서 동작하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.609-612
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• 2002

본 논문은 다양한 멀티미디어 응용을 위한 재구성가능(reconfigurable) 구조의 프로세서 설계에 대해서 연구하였다. 설계된 프로세서는 RISC 코어 프로세서와 코스-그레인(coarse-grain) 구조의 재구성가능 셀들의 배열로 이루어진 처리 유닛으로 구성되었다. 여기서 사용된 RISC 코어 프로세서는 하드웨어 구조를 간단히 하기 위하여 MIPS 명령어들 중에서 사용빈도가 높은 것들만 고려하였으며, 재구성가능 처리를 위한 별도의 명령어를 추가하였다. 본 논문에서 제시한 재구성가능 프로세서는 VHDL로 모델링하여 실행을 검증하였으며, 하드웨어의 유연성을 증가하여 다양한 멀티미디어 응용에 적용함과 아울러 속도향상에 기여함을 볼 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.10-21
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• 1997

In this paper, we propose multiple instruction issuable multi-streaming as a processor architecture for 3D graphics processor. Multistreaming can eliminate inteferences within concurrently executing instructions inthe pipelined processor to allow enough parallelism for parallel processing. Through cycle level simulation study, we show that the proposed architecture outperforms a conventional RISC processor, MIPS R3000 by three times with reasonable resource overheads. Multiple instruction issuable multistreaming processor will be a bood architecture for instruction processor when a large number of threads are guaranteed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.770-776
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• 2004

The goal of perceptual audio coder is to reduce redundancy and irrelevancy of audio signal based on the concept of masking. Several studies on masking effect reveal that the masking threshold varies as a function of the noise-like or tone-like nature of audio signals. Therefore, tonality of audio signal influences significantly the quality and efficiency of perceptual audio coder In this paper, we propose a new effective algorithm for tonality measure using spectrum energy. Since the proposed algorithm consists of a few transcendental functions and simple operations, it has lower complexity than MPEG psychoacoustic model-II. The proposed algorithm was tested with some audio signals, and DSP implementation showed that the proposed algorithm could be implemented with 3 MIPS. These results illustrate the efficiency of proposed algorithm in both performance and complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.63-71
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• 2002

This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.