• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.743-746
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• 2000

Metal-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/$LiNbO_3$/Si structure were successfully fabricated. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V) curve was about 8.2. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$$1O^{-8}$A/$cm^2$ order at the electric field of 500kV/cm. The dielectric constant of $LiNbO_3$film on AIN/Si structure was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500kV/cm was about 5.6$\times$ $1O^{13}$ $\Omega$.cm.

• 한국세라믹학회지
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• 제42권9호
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• pp.624-630
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• 2005

To investigate the possibility of the $ZrO_2$ buffer layer as the insulator for the Metal-Ferroelectric-Insulator-semiconductor (MFIS) structure, $ZrO_2$ and $SrBi_2Ta_2O_9$ (SBT) thin films were deposited on the P-type Si(111) wafer by the R.F. magnetron-sputtering method. According to the process with and without the post-annealing of the $ZrO_2$ buffer layer and SBT thin film, the diffusion amount of Sr, Bi, Ta elements show slight difference through the Glow Discharge Spectrometer (GDS) analysis. From X-ray Photoelectron Spectroscopy (XPS) results, we could confirm that the post-annealing process affects the chemical binding condition of the interface between the $ZrO_2$ thin film and the Si substrate. Compared to the MFIS structure without the post-annealing of the $ZrO_2$ buffer layer, memory window value of MFlS structure with post-annealing of the $ZrO_2$ buffer layer were considerably improved. The window memory of the Pt/SBT (260 nm, $800^{\circ}C)/ZrO_2$ (20 nm) structure increases from 0.75 to 2.2 V under the applied voltage of 9 V after post-annealing.

• 한국세라믹학회지
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• 제40권1호
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• pp.52-61
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• 2003

R.F 마그네트론 스퍼터링법으로 ZrO$_2$ 확산 방지막과 SrBi$_2$Ta$_2$$O_{9}$ 강유전 박막을 증착하여 MFIS 구조론 제작하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해서 일반 분리기로와 RTA로에서 각각 산소 분위기와 아르곤 분위기에서 550~85$0^{\circ}C$의 온도범위에서 후열처리를 행한 후, C-V 특성 및 누설전류 특성을 분석하였다. RTA 75$0^{\circ}C$ 산소 분위기에서 후열처리된 20nm의 두께를 가지는 ZrO$_2$ 박막에서 최대의 메모리 윈도우 값을 얻었다. Pt/SBT(260nm)ZrO$_2$(20nm)/Si 구조는 Pt/SBT(260nm)/Si 구조의 값보다 C-V 특성 및 누설전류 특성이 우수하였으며 이러한 결과는 ZrO$_2$ 박막이 SBT와 Si사이에서 우수한 완충층의 역할을 함을 알 수 있었다.

• 한국진공학회지
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• 제7권3호
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• pp.195-200
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• 1998

본 연구에서는 강유전체 박막의 게이트 산화물로 사용한 $Pt/SrBi_2Ta_2O_9(SBT)/CeO_2/Si(MFS)$와 Pt/SBT/Si(MFS) 구조의 결정 구조 및 전기적 성질 의 차이를 연구하였다. XRD 및 SEM 측정 결과 SBT/$CeO_2$/Si박막은 약5nm정도의 $SiO_2$층 이 형성되었고 비교적 평탄한 계면의 미세구조를 가지는 반면, SBT/Si는 각각 약6nm와 7nm정도의 $SiO_2$층과 비정질 중간상층이 형성되었음을 알 수 있다. 즉 CeO2 박막을 완충층 으로 사용함으로써 SBT박막과 Si기판의 상호 반응을 적절히 억제할 수 있음을 확인하였다. Pt/SBT/$CeO_2/Pt/SiO_2$/와 Pt/SBT/Pt/$SiO_2$/Si구조에서 Polarization-Electric field(P-E) 특 성을 비교해 본 결과 CeO2박막의 첨가에 따라 잔류분극값은 감소하였고 항전계값은 증가하 였다. MFIS구조에서 memory window값은 항전계값과 직접적 관련이 있으므로 이러한 항 전계값의 증가는 MFIS구조에서의 memory window값이 증가할 수 있음을 나타낸다. Pt-SBT(140nm)/$CeO_2$(25nm)/Si구조에서 Capacitance-Voltage(C-V) 측정 결과로부터 동작 전압 4-6V에서 memory wondows가 1-2V정도로 나타났다. SBT박막의 두께가 증가할수록 memory window값은 증가하였는데 memory wondows가 1-2V정도로 나타났다. SBT박막의 두께가 증가할수록 memory window값은 증가하였는데 이는 SBT박막에 걸리는 전압강하가 증가하기 때문인 것으로 생각되어진다. Pt/SBT/$CeO_2$/Si의 누설전류는 10-8A/cm2정도였고 Pt/SBT/Si 구조에서는 약10-6A/cm2정도로 약간 높은 값을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.734-737
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• 2004

The metal-ferroelectric-semiconductor (MFS) structure is widely studied for nondestructive readout (NDRO) memory devices, but conventional MFS structure has a critical problem. It is difficult to obtain ferroelectric films like PZT on Si substrate without interdiffusion of impurities such as Pb, Ti and other elements. In order to solve these problems, the metal-ferroelectric-insulator-semiconductor (MFIS) structure has been proposed with a buffer layer of high dielectric constant such as MgO, $Y_2O_3$, and $CeO_2$. In this study, the etching characteristics (etch rate, selectivity) of MgO thin films were etched using $Cl_2/Ar$ plasma. The maximum etch rate of 85 nm/min for MgO thin films was obtained at $Cl_2$(30%)/Ar(70%) gas mixing ratio. Also, the etch rate was measured by varying the etching parameters such as ICP rf power, dc-bias voltage, and chamber pressure. Plasma diagnostics was performed by Langmuir probe (LP) and optical emission spectroscopy (OES).

• 한국재료학회지
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• 제10권12호
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• pp.807-811
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• 2000

MFISFET (Metal-ferroelectric-nsulator-semiconductor-field effect transistor)에의 적용을 위해 CeO$_2$와 SrBi$_2$Ta$_2$O$_{9}$ 박막을 각각 r.f. sputtering 및 pulsed laser ablation법으로 제조하였다. CeO$_2$ 박막은 증착시 스퍼터링개스비 (Ar:O$_2$)에 따른 특성을 고찰하였다. Si(100) 기판 위에 $700^{\circ}C$에서 증착된 CeO$_2$ 박막들은 (200)방향으로 우선방향성을 가지고 성장하였고 $O_2$ 개스량이 증가함에 따라 박막의 우선방향성, 결정립도 및 표면거칠기는 감소하였다. C-V특성에서는 Ar:O$_2$가 1 : 1인 조건에서 제조된 박막이 가장 양호한 특성을 보였다. 제조된 박막들의 누설전류값은 100kV/cm의 전계에서 $10^{-7}$ ~$10^{-8}$ A의 차수를 보였다. CeO$_2$/Si 기판위에 성장된 SBT는 다결정질상의 치밀한 구조를 가지고 성장을 하였다 80$0^{\circ}C$에서 열처리된 SBT박막으로 구성된 MFIS구조의 C-V 특성에서 memory window 폭은 0.9V를 보였으며 5V에서 4$\times$$10^{-7}$ A/$\textrm{cm}^2$의 누설전류밀도를 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.