• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.297-300
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• 2000

This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by “Radix-4/2”, uses the feature of existing radix-2$^3$algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 campared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2$^3$algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2$^3$algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's.