A High Speed and Area Efficient FFT Algorithm and Its Hardware Implementation

고속 및 면적 효율적인 FFT 알고리즘 개발 및 하드웨어 구현

This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by “Radix-4/2”, uses the feature of existing radix-2$^3$algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 campared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2$^3$algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2$^3$algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's.