• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1332-1339
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• 2000

This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.906-912
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• 2012

A ship ad-hoc network (SANET) can provide ships with diverse multimedia services by replacing expensive satellite communications. While ITU-R M. 1842-1, standards for maritime VHF band digital communications, can be used as the specifications of physical layer for SANETs, no standards are specified for higher layers of SANETs. In this paper, we propose a ship ad-hoc communication (SAC) protocol for SANETs, based on medium access control (MAC) and routing protocols for terrestrial ad-hoc networks. SAC protocol is a cross-layer protocol which combines MAC and routing into one algorithm and considers maritime environments, including the existence of neighboring ships, the possibility of routing to a destination, and changing the communication mode in case of VHF channel failure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1155-1163
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• 2010

An algorithm of the conventional wavelet shift keying is carried out that the scaling function and wavelet are encoded to 1(mark) and 0(space) for the input binary data, respectively. Two bit modulation technique which uses four carrier frequencies is existed. Four carrier frequencies are defined as scaling function, inversed scaling function, wavelet, and inversed wavelet, which are encoded to 10, 11, 00 and 01, respectively. In this paper, we defined 4-ary SWSK (4-ary scaling wavelet shift keying) which is two bit modulation, and it is derived to the probability of bit error and symbol error of the defined system from QPSK. In order to analyze to the performance of 4-ary SWSK, we are obtained in terms of the probability of bit error and symbol error for QPSK (quadrature phase shift keying), MFSK(M-ary frequency shift keying) and proposed method. As a results of simulation, we confirmed that the proposed method was superior to the performance in terms of the probability of bit error and symbol error.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.165-171
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• 2004

Owing to small sizes and high density to the semiconductor It, it is difficult to discriminate the defects of ICs by human eyes. High precision inspection system with computer vision is essentially established for the manufacturing process due to the variety of defective parts. Especially it is difficult to implement the algorithm for the coplanarity of IC leads. Therefore in this paper, the inspection system which can detect the defects of the SOP types of ICs having 1cm${\times}$0.5cm of the chip size is implemented and evaluated it's performance. In order to optimally detect various items, some principles of geometry are theoretically presented , length measurement, pitch measurement, angle measurement, brightness of image and correcton of position. The interface circuit is designed for implementation of inspection system and connected the HANDLER. In the result, the system could detect two ICs' defects per second and confirmed the resolution of 20$\mu$m per pixel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2162-2166
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• 2016

This paper describes the implementation of AUSV system for sonar image acquisition to survey the seabed. The system is controlled by Feed Forward PID algorithm on the vessel for bearing of the thrusters composed of motion sensor and DGPS which calculates the differences between the current location and the destination location for longitude and latitude based on GPS coordinates. As experimental results, the bearing control performance is good that the error distance from the destination positions are under 6m in total survey track of 1km. And the sonar image deviation of a object is under 12 pixels from the manned survey method, which the comparison with the total image quality is almost the same as the manned survey one. Thus the proposed AUSV system is a new method of system can be utilized at the limited survey areas as the surveyor should not be able to approach on sea surface by onboard vessel.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.514-517
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• 2017

In solar photovoltaic systems, power generation is greatly affected by the weather conditions, so it is essential to predict solar energy for stable load operation. Therefore, data on weather conditions are needed as inputs to machine learning algorithms for solar energy prediction. In this paper, we use 15 kinds of weather data such as the precipitation accumulated during the 3 hours of the surface, upward and downward longwave radiation average, upward and downward shortwave radiation average, the temperature during the past 3 hours at 2 m above from the ground and temperature from the ground surface as input data to the algorithm. We analyzed the statistical characteristics and correlations of weather data and extracted the downward and upward shortwave radiation averages as a major elements of a feature vector with high correlation of 70% or more with solar energy.

• Proceedings of the Korean Institute of Resources Recycling Conference
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• 2005.05a
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• pp.57-61
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• 2005

In this study, the machine vision system for inspection using color recognition method have been designed and developed to automatically sort out a specified material such as Cu scraps or other non-ferrous metal scraps mixed in Fe scraps. The system consists of a CCD camera, light sources, a frame grabber, conveying devices and an air nozzled ejector, and is program-controlled by a image processing algorithm. The ejector is designed to be operated by an I/O interface communication with a hardware controller. The sorting examination results show that the efficiency of separating Cu scraps from the Fe scraps mixed with Cu scraps is around 90 % at the conveying speed of 15 m/min. and the system is proven to be excellent in terms of its efficiency. Therefore, it is expected that the system can be commercialized in shredder firms, if the high-speed automated sorting system will be realized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1739-1747
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• 2004

In this paper, an efficient radix-4 systolic VLSI architecture for RSA public-key cryptosystem is proposed. Due to the simple operation of iterations and the efficient systolic mapping, the proposed architecture computes an n-bit modular exponentiation in n$^{2}$ clock cycles since two modular multiplications for M$_{i}$ and P$_{i}$ in each exponentiation process are interleaved, so that the hardware is fully utilized. We encode the exponent using Radix-4. SD (Signed Digit) number system to reduce the number of modular multiplications for RSA cryptography. Therefore about 20% of NZ (non-zero) digits in the exponent are reduced. Compared to conventional approaches, the proposed architecture shows shorter period to complete the RSA while requiring relatively less hardware resources. The proposed RSA architecture based on the modified Montgomery algorithm has locality, regularity, and scalability suitable for VLSI implementation.