• Journal of Power Electronics
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• 제11권2호
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• pp.132-139
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• 2011

The selective harmonic elimination pulse width modulation (SHEPWM) switching strategy has been applied to multilevel inverters to remove low harmonics. Naturally, the related equations do not have feasible solutions for some operating points associated with the modulation index (M). However, with these infeasible points, minimizing instead of eliminating harmonics is performed. Thus, harmful harmonics such as the $5^{th}$ harmonic still remains in the output waveform. Therefore, it is proposed in this paper to ignore solving the equation associated with the highest order harmonics. A reduction in the eliminated harmonics results in an increase in the degrees of freedom. As a result, the lower order harmonics are eliminated in more operating points. A 9-level inverter is chosen as a case study. The genetic algorithm (GA) for optimization purposes is used. Simulation results verify the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.1978-1981
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• 1997

This paper describes several PWM method for harmonics reduction in GTO inverter. The analysis and simulations of PWM techniques are carried out. The simulation results demonstrate that the programmed PWM methods(SHE PWM) are superior to the sine-modulated PWM method. The selected harmonic elimination (SHE) PWM scheme which eliminates specific lower order harmonics can generate high quality output waveform in PWM inverter.

• Journal of Power Electronics
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• 제17권6호
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• pp.1672-1682
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• 2017

For grid-connected LCL-filtered inverters, the inverter-side current can be used as the control object with one current sensor for both LCL resonance damping and over-current protection, while the grid-voltage feedforward or harmonic resonant compensator is used for suppressing low-order grid current harmonics. However, it was found that the grid current harmonics were high and often beyond the standard limitations with this control. The limitations of the inverter-side current control in suppressing low-order grid current harmonics are analyzed through inverter output impedance modeling. No matter which compensator is used, the maximum magnitudes of the inverter output impedance at lower frequencies are closely related to the LCL parameters and are decreased by increasing the control delay. Then, to improve the grid current quality without complicating the control or design, this study proposes designing the filter capacitance considering the current harmonic constraint and using a PWM mode with a short control delay. Test results have confirmed the limitation and verified the performance of the improved approaches.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권2호
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• pp.68-79
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• 2003

We estimated harmonics on power system of AC railway based on quantitatively measured harmonics and investigated the need of facilities for harmonics reduction. In order to analysis harmonics which inflow into power system due to increase in collector voltages and harmonic currents generated from the train when the railway is in operation, the railway system Is sectioned into power supply, railway line, AT, sectioning Post and subsectioning post. For analysis of extension of currents resulting from the railway loads, PWM converter, VVVF inverter and the feeder system are modeled based on the dynamic node technique(DNT). In order to test the usefulness of the DNT for analysis of harmonic effects, the measured harmonic currents and harmonic magnification ratios at the S/K substation are compared with simulation results using DNT modelling, which include the results for two cases with and without filters for suppression of harmonic currents. When 8 cars(4M4T) are in operation, the total sum of harmonic currents resulting from the train at M and T phases, which inflow into the substation along with the railway line, is calculated. Using the harmonics analysis program for railway feeder system with these data, the total harmonic distortion factor(710) at the outgoing point of KEPCO substation is computed. The calculation shows that when the maximum THD at the receiving point of H/K substation was 0.0443% which is much lower than 1.5% which is the allowable value of KEPCO at 154kV as well as IEEE-519 above 132kV This result indicates that any measure for harmonics reduction in Incheon International Airport Railway is not needed.

• 전기학회논문지P
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• 제58권2호
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• pp.148-153
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• 2009

As the increasing of non-linear load, we have a growing interest in power quality. Power quality has come to the voltage quality. Voltage harmonics consist in at the PCC by the non-linear load. Capacitor is generally used for the power compensation and as the passive filter by the serial connection with reactor. Capacitor has low impedance as the frequency increases, so easily fall down by the harmonic component of non-linear load. Small voltage of low-order acts on quite a few at the capacitor by the current increase. In this paper, we measured the magnitude and angle of voltage at the PCC and calculated under the same condition. we checked out that lower voltage of higher order produces current magnification.

• 대한전자공학회논문지TC
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• 제48권1호
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• pp.50-54
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• 2011

본 논문에서는 고출력 증폭기의 출력 정합단에서 발생하는 2차, 3차 고조파 성분을 억제하여 단일 고출력 증폭기의 선형성을 개선시키고 $3^{rd}$ IMD의 전치 왜곡에 의한 선형성 개선 PAM (Power Amplifier Module)을 제안하였다. 고조파를 억제하기 위해 정합회로는 메타전자파 구조를 갖도록 설계되었으며 2, 3차 고조파가 각각 27 dBc 이상 억제되었다. $3^{rd}$ IMD의 전치 왜곡은 구동 증폭기에서 발생하는 $3^{rd}$ IMD의 위상을 조절하여 -30도가 되도록 하였으며 이때 고출력 증폭기에서 발생되는 $3^{rd}$ IMD와 상쇄를 일으켜 고출력 증폭기 보다 6 dBc 이상 개선된 고조파 성분을 갖도록 설계되었다. 제안된 PAM은 36.98 dBm의 출력 전력과 21.6 dB의 전력 이득, 29.4 %의 전력 효율을 얻었으며 2차 고조파가 -53 dBc로 참조 증폭기에 비해 20dBc 이상 억제되는 특성을 얻었다.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2007년도 춘계학술대회 논문집
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• pp.468-472
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• 2007

For small capacity rectifier circuits such as these for consumer electronics and appliances, capacitor input type rectifier circuits are generally used. Consequently, various harmonics generated within the power system become a serious problem. Various studies of this effect have been presented previously. The absence of switching devices makes systems more tolerant to over-load, and brings low radio noise benefits. We propose a power factor correction scheme using a LC resonant in commercial frequency without switching devices. In this method, It makes a sinusoidal wave by widening conduction period using the current resonance in commercial frequency, Hence, the harmonic characteristics can be significantly improved, where the lower order harmonics, such as the fifth and seventh orders are much reduced. The result are confirmed by the theoretical and expermental implementations

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.233-235
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• 2001

On the active filter converter for power factor correction is used inverter for a air-conditioner's power supply to meet IEC standard In the active filter topology for power factor correction, extra switch only control the input current indirectly to satisfied with the IEC standard for reducing the cost and size. In this paper, by dividing the input current into two different modes, the current conduction period can be widened and harmonics can largely be canceled between the two modes. Hence, the harmonics characteristics can be significantly improved, whereby the lower order harmonics, such as the fifth and seventh orders, are much reduced. The results are confirmed by theoretical and experimental implementations.

• 전력전자학회논문지
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• 제9권1호
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• pp.58-64
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• 2004

본 논문에서는 직류를 전원으로 하는 지하철에서 직류모선의 잉여전력을 교류모선으로 회생할 수 있는 직류전력 회생시스템의 고조파를 저감시키는 새로운 제어기법을 제안하였다. 직류전력 회생시스템에 수정 a도통(MAC : Modified a-Conduction)방식을 적용하면 출력전압에 12k$\pm$1차의 고조파가 존재한다. 이에 반해 본 논문에서 제안하는 SHE(Selected Harmonic Elimination)에 기반을 둔 방식을 적용하면 11차 고조파와 13차 고조파가 추가로 제거된다. 또한 회생시스템의 출력단에 23차 교류필터를 설치하면 잔존하는 고조파중 최저차 고조파인 23차 고조파도 제거할 수 있다. 본 논문에서 제안한 SHE방식을 적용한 고조파 저감기법을 검증하기 위하여 축소모델을 대상으로 하여 시뮬레이션을 행하였다. 그 결과, 출력전압의 THD가 기존의 MAC방식보다 더 낮으며 제어범위에서의 THD가 0.53∼0.68(%) 범위임을 확인하였다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권6호
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• pp.285-291
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• 2002

In general, utility voltage is maintained at a relatively low level of Phase unbalance since a low level of unbalance can cause a significant power supply ripple and heating effects on the power system equipment. Voltage unbalance more commonly emerges in individual customer loads due to phase load unbalanced, especially where single phase power loads are used. Under unbalanced input voltages large lower order harmonics appears at the input and output ports of Power conversion devices. As the application of adjustable -speed drives (ASDs) and their integration with complex industrial processes increase, so does the need to understand how ASDs perform during voltage This paper describes a real load test to investigate the performance of 3-HP adjustable speed drives by an unbalanced voltage at the low-voltage system.