• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.642-649
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• 2006

In order to recognize a situation from a environment which provides an intelligent service, we propose state-transition based situation modeling which is suitable for a low computing power and restricted resources like embedded systems, and we designed its application to a situation-action converter(SAC)which is consist of two parts; situation detector recognized wanted situations and action generator generated various control actions. Then, we implemented a situation manager for smart scheduler service by using a SAC which is installed to a ARM processor based embedded Linux evaluation board.

• ETRI Journal
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• v.35 no.4
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1015-1018
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• 2005

This study intended to demonstrate a general system as an web server implemented by pure software solution and focused on collecting data by remote control through Internet and constructing its' control frame. To achieve these, this study suggested an optimized, low-power, ultra tiny embedded web server. When unpredictable accidents, such as heat sensor or industrial disasters, happen, it will connect sensors collecting building information each other by network and obtain final results via web porting, web hardware control or porting, or hardware test process in a boot loader on the basis of StrongARM SA-1110 processor.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.101-106
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• 2015

We designed, developed and characterized a multi-segmented tissue equivalent proportional (TEPC) counter for microdosimetry. The energy resolution of the multi-segmented TEPC was about 12% for $^{241}Am$ 5.45 MeV alpha particles. The resolution was better than 33% for a single un-segmented TEPC. A compact and low power consumption TEPC could be made by using digital pulse processor (DPP). We also successfully calibrated the TEPC by using $^{252}Cf$ standard neutron source in Korea Research Institute of Standards and Science (KRISS). According to the results, the TEPC is useful for several application of radiation monitoring such as a neutron monitor, air crew monitor and space dosimeter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.326-330
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• 2020

Small-scale production control systems for smart manufacturing are becoming increasingly necessary as the manufacturing industry seeks to maximize manufacturing efficiency as the demand for customized product production increases. Correspondingly, the development of an embedded system to realize this capability is becoming important. In this study, we developed an embedded system based on an open source system that is cheaper than a widely applied programmable logic controller (PLC)-based production control system that is easier to install, configure, and process than a conventional relay control panel. This embedded system is system is based on a low-power, high-performance Cortex M4 processor and can be applied to smart manufacturing. It is designed to improve the development environment and compatibility of existing PLCs, control small-scale production systems, and enable data collection through heterogeneous communication. The real-time response characteristics were confirmed through an operation test for input/output control and data collection, and it was confirmed that they can be used in industrial sites.

• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.6
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• pp.562-567
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• 2000

Many pressure vessels for power and industrial plant are fabricated from low alloy carbon steels. The inner sides of pressure vessels are commonly weld-cladded with austenitic stainless steels to minimize problems of corrosive attack. Disbonding cracks are often detected at the transition region of welding interlayer, which is serious problem to reliability of pressure vessels. We have developed C-scan system to high speed inspection of overlay weld using DSP(digital signal processor). This system consists of signal processing parts (oscilloscope, pulser/receiver, digitizer, DSP), scanner, program and position controller. The developed system has been applied to a practical ultrasonic testing in overlay weld, and demonstrated high speed with precision

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.528-539
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• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• The KIPS Transactions:PartA
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• v.14A no.6
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• pp.347-356
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• 2007

In designing a branch predictor, in addition to accuracy, microarchitects should consider power consumption, especially for embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB (Branch Target Buffer) only when the prediction from the PHT (Pattern History Table) is taken. To enable the selective access to the BTB, the PHT in the proposed branch predictor is accessed one cycle earlier than the traditional PHT to prevent the additional delay. As a side effect, two predictions from the PHT are obtained through one access to the PHT, which leads to more power savings. The proposed branch predictor reduces the power consumption, not requiring any additional storage arrays, not incurring additional delay (except just one MUX delay) and never harming accuracy. Simulation results show that the proposed predictor reduces the power consumption by $35{\sim}48%$ compared to the traditional predictor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.1
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• pp.61-71
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• 2018

In the Internet of Things, in which plenty of devices have connection to each other, cryptographically secure Random Number Generators (RNGs) are essential. Particularly, entropy source, which is the only one non-deterministic part in generating random numbers, has to equip with an unpredictable noise source(or more) for the required security strength. This might cause an requirement of additional hardware extracting noise source. Although additional hardware resources has better performance, it is needed to make the best use of existing resources in order to avoid extra costs, such as area, power consumption. In this paper, we suggest an entropy source which uses a multi-threaded program without any additional hardware. As a result, it reduces the difficulty when implementing on lightweight, low-power devices. Additionally, according to NIST's entropy estimation test suite, the suggested entropy source is tested to be secure enough for source of entropy input.