• ETRI Journal
• /
• 제34권2호
• /
• pp.268-271
• /
• 2012

The high peak-to-average power is one of the main drawbacks in OFDM systems. This letter proposes a partial shift mapping (PSM) method for peak power reduction in OFDM systems. By utilizing the properties of the discrete Fourier transform, the proposed method generates a set of candidate signals without additional complex multiplication and selects the one with minimum peak power for transmission. Analyses and simulations confirm that the PSM method achieves satisfactory peak power reduction performance and low complexity compared with other kindred methods, for example, selected mapping and partial transmit sequences.

• 한국정보통신학회논문지
• /
• 제22권9호
• /
• pp.1257-1263
• /
• 2018

경량 사물인터넷 디바이스 상에서의 암호화 구현은 정확하고 빠르게 연산을 수행하여 서비스의 가용성을 높이는 것이 중요하다. 특히 곱셈 연산은 RSA, ECC, 그리고 SIDH와 같은 공개키 암호화에 활용되는 핵심 연산으로 최적화된 구현이 요구된다. 하지만 최신 저전력 프로세서인 ARM Cortex-M3 프로세서의 경우에는 곱셈연산 입력 크기에 따라 수행속도가 달라지는 보안 취약점을 가지고 있다. 수행속도가 달라지게 될 경우 연산 시간의 차이점을 확인하여 비밀정보를 추출하는 것이 가능하다. 이를 보완하기 위해 최근 연구에서는 고정된 연산 시간 안에 곱셈 연산을 수행하는 기법이 제안되었다. 하지만 해당 구현에서는 여전히 속도가 완전히 최적화되어 있지 않다. 본 논문에서는 기존에 제안된 곱셈연산을 보다 효율적으로 연산하기 위한 기법을 제안한다. 제안된 기법은 기존 방식에 비해 연산 속도를 최대 25.7% 향상시킨다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.321-324
• /
• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• 한국전자통신학회논문지
• /
• 제17권1호
• /
• pp.173-180
• /
• 2022

근사 컴퓨팅은 효율적인 하드웨어 컴퓨팅 시스템을 설계하기 위한 유망한 방법이다. 근사 곱셈은 고성능, 저전력 컴퓨팅을 위한 근사 계산 방식에 사용되는 핵심적인 연산이다. 근사 4-2 compressor는 근사 곱셈을 위한 효율적인 하드웨어 회로를 구현할 수 있다. 본 논문에서는 저면적, 저전력 특성을 갖는 근사 곱셈기를 제안하였다. 근사 곱셈기 구조는 정확한 영역, 근사 영역, 상수 수정 영역의 세 영역으로 나누어진다. 새로운 4:2 근사 compressor를 사용하여 근사 영역의 부분 곱 축소를 단순화하고, 간단한 오류 수정 방식을 사용하여 근사로 인한 오류를 보상한다. 상수 수정 영역은 오차를 줄이기 위해 확률 분석을 통한 상수를 사용하였다. 8×8 곱셈기에 대한 실험 결과, 제안한 근사 곱셈기는 기존의 4-2 compressor 기반의 근사 곱셈기보다 적은 면적을 요구하면서 적은 전력을 소비함을 보였다.

• 한국정보전자통신기술학회논문지
• /
• 제11권3호
• /
• pp.270-276
• /
• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.263-264
• /
• 2006

In this paper, an efficient and fast algorithm to reduce calculation amount of FIR(Finite Impulse Responses) filtering is proposed. Proposed algorithm enables arbitrary size of parallel processing, and their structures are also easily derived. Furthermore, it is shown that the number of multiplication/sample is reduced, and number of instructions using MAC(Multiplication and Accumulation) processor are also reduced. For theoretical improvement, numbers of sub filters are compared with those of conventional algorithm. In addition to the theoretical improvement, it is shown that number of element for hardwired implementation are reduced comparison to those of the conventional algorithm.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제54권2호
• /
• pp.124-130
• /
• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.414.2-414.2
• /
• 2016

The optimal configuration of a transmutation reactor based on a low aspect ratio tokamak is determined using coupled analysis of tokamak systems and neutron transport. The inboard radial build of the reactor components is obtained from plasma physics and engineering constraints, while outboard radial builds are mainly determined by constraints on a neutron multiplication, a tritium-breeding ratio, and a power density. It is shown that a breeding blanket model has an impact on the radial build of a transmutation blanket. A burn cycle has to be determined to limit a fast neutron fluence of a plasma facing material below a radiation damage limit.

• 한국정보처리학회:학술대회논문집
• /
• 한국정보처리학회 2009년도 추계학술발표대회
• /
• pp.405-406
• /
• 2009

4-2 compressor는 곱셈기의 부분 곱 합 트리(partial product summation tree)의 기본적인 구성요소이다. 본 논문은 저 전력 특성을 갖는 4-2 compressor 구조를 제안한다. 제안한 회로는 한 개의 전가산기와 MUX로 구성하였다. 이 회로는 기존의 회로와 비교하였을 때 회로 구성에 필요한 트랜지스터수가 14개 감소하였으며, 6.3%의 전력소모가 감소하였다. 제안한 회로는 Samsung 0.18um CMOS 공정을 이용하여 HSPICE로 시뮬레이션 하였다.